Investigation of gate oxide traps effect on NAND flash memory by TCAD simulation<xref rid="cpb_29_3_038501fn1" ref-type="fn">*</xref><fn id="cpb_29_3_038501fn1"><label>*</label><p>Project supported by the SanDisk Info Tech Shanghai, China and the Institute of Microelectronic Materials & Technology, School of Materials Science and Engineering, Shanghai Jiao Tong University, China.</p></fn>

Investigation of gate oxide traps effect on NAND flash memory by TCAD simulation**

Project supported by the SanDisk Info Tech Shanghai, China and the Institute of Microelectronic Materials & Technology, School of Materials Science and Engineering, Shanghai Jiao Tong University, China.

Zhang He-Kun¹, Tian Xuan², He Jun-Peng¹, Song Zhe², Yu Qian-Qian², Li Liang², Li Ming¹, Zhao Lian-Cheng¹, Gao Li-Ming^{1, †}

Gate leakage currents varying with gate bias under different trap conditions in erase process: (a) different trap densities in blocking layer at 2 eV and (b) different trap densities in tunneling layer at 2 eV.