Investigation of gate oxide traps effect on NAND flash memory by TCAD simulation*

Project supported by the SanDisk Info Tech Shanghai, China and the Institute of Microelectronic Materials & Technology, School of Materials Science and Engineering, Shanghai Jiao Tong University, China.

Zhang He-Kun1, Tian Xuan2, He Jun-Peng1, Song Zhe2, Yu Qian-Qian2, Li Liang2, Li Ming1, Zhao Lian-Cheng1, Gao Li-Ming1, †
       

(a) Plots of Vt shift versus program time at different trap densities, and (b) plots of trapped charge versus gate bias at different trap densities in program process.