Investigation of gate oxide traps effect on NAND flash memory by TCAD simulation
Project supported by the SanDisk Info Tech Shanghai, China and the Institute of Microelectronic Materials & Technology, School of Materials Science and Engineering, Shanghai Jiao Tong University, China.
(a) Gate leakage currents varying with gate bias in erase process at different trap energies, and (b) trapped charges changing with gate bias at different trap densities in erase process.
