Negative gate bias stress effects on conduction and low frequency noise characteristics in p-type poly-Si thin-film transistors
Han Chao-Yang1, 2, 3, Liu Yuan2, 3, †, Liu Yu-Rong1, Chen Ya-Yi1, 2, 3, Wang Li1, 2, 3, Chen Rong-Sheng1
       

Variations of trap density versus stress voltage ( Δ N = Δ N it − Δ N ox ).