Negative gate bias stress effects on conduction and low frequency noise characteristics in p-type poly-Si thin-film transistors
Han Chao-Yang1, 2, 3, Liu Yuan2, 3, †, Liu Yu-Rong1, Chen Ya-Yi1, 2, 3, Wang Li1, 2, 3, Chen Rong-Sheng1
       

Log–log plot of Δ V th versus stress time in poly-Si TFTs with different bias stress voltages.