Analysis of tail bits generation of multilevel storage in resistive switching memory

Liu Jing^{1, 2}, Xu Xiaoxin^{1, 2, †}, Chen Chuanbing^{1, 2}, Gong Tiancheng^{1, 2}, Yu Zhaoan², Luo Qing², Yuan Peng^{1, 2}, Dong Danian², Liu Qi², Long Shibing², Lv Hangbing^{2, ‡}, Liu Ming²

(color online) Retention characteristics of IRS at 200 °C. For (a) IRS-1 and (b) IRS-2, both tail bits (1) and tail bits (2) are detected. The tail bits deteriorate at higher baking temperatures.