Analysis of tail bits generation of multilevel storage in resistive switching memory

Liu Jing^{1, 2}, Xu Xiaoxin^{1, 2, †}, Chen Chuanbing^{1, 2}, Gong Tiancheng^{1, 2}, Yu Zhaoan², Luo Qing², Yuan Peng^{1, 2}, Dong Danian², Liu Qi², Long Shibing², Lv Hangbing^{2, ‡}, Liu Ming²

(color online) Tendency chart of the typical distribution of IRS^S and IRS^R as bake time increases: (a) IRS^S contains tail bits (1) without any tail bits (2) and (b) IRS^R mainly suffers from tail bits (2), accompanied by several tail bits (1).