Analysis of tail bits generation of multilevel storage in resistive switching memory

Liu Jing^{1, 2}, Xu Xiaoxin^{1, 2, †}, Chen Chuanbing^{1, 2}, Gong Tiancheng^{1, 2}, Yu Zhaoan², Luo Qing², Yuan Peng^{1, 2}, Dong Danian², Liu Qi², Long Shibing², Lv Hangbing^{2, ‡}, Liu Ming²

(color online) Tail bits of IRS data retention: (a) tail bits (1) in IRS-1 after 15-h baking at 110 °C and (b) IRS-2 with two types of tail bits. Historical records of the operations of these bits indicate that most of them stem from IRS^S.