Analysis of tail bits generation of multilevel storage in resistive switching memory

Liu Jing^{1, 2}, Xu Xiaoxin^{1, 2, †}, Chen Chuanbing^{1, 2}, Gong Tiancheng^{1, 2}, Yu Zhaoan², Luo Qing², Yuan Peng^{1, 2}, Dong Danian², Liu Qi², Long Shibing², Lv Hangbing^{2, ‡}, Liu Ming²

(color online) (a) Schematic of 1-kb RRAM array. The SET operation is executed by applying voltage bias on BL. For RESET operation, voltage is applied on SL. (b) Multilevel storage is achieved in the 1-kb array by either SET operation or RESET operation.