Key technologies for dual high-<i>k</i> and dual metal gate integration<xref rid="cpb_27_9_097306fn1" ref-type="fn">*</xref><fn id="cpb_27_9_097306fn1"><label>*</label><p>Project supported by the National High Technology Research and Development Program of China (Grant No. 2015AA010601).</p></fn>

Key technologies for dual high-k and dual metal gate integration**

Project supported by the National High Technology Research and Development Program of China (Grant No. 2015AA010601).

Li Yong-Liang^†, Xu Qiu-Xia, Wang Wen-Wu

Separating of high-k and metal gate for n/pMOS. (a) TaN/Mo/HfSiAlON deposition after selectively removing TaN/HfSiON, (b) TaN/Mo/HfSiAlON selectively removing, (c) a-Si hardmask removing, and (d) Poly-Si capping.