Influence of dopant concentration on electrical quantum transport behaviors in junctionless nanowire transistors<xref rid="cpb_27_8_088106_fn1" ref-type="fn">*</xref><fn id="cpb_27_8_088106_fn1"><label>*</label><p>Project supported by the National Key Research and Development Program of China (Grant No. 2016YFA0200503), the Program for Innovative Research Team (in Science and Technology) in University of Henan Province, China (Grant No. 18IRTSTHN016), and the National Natural Science Foundation of China (Grant Nos. 61376096, 61327813, and 61404126).</p></fn>

Influence of dopant concentration on electrical quantum transport behaviors in junctionless nanowire transistors**

Project supported by the National Key Research and Development Program of China (Grant No. 2016YFA0200503), the Program for Innovative Research Team (in Science and Technology) in University of Henan Province, China (Grant No. 18IRTSTHN016), and the National Natural Science Foundation of China (Grant Nos. 61376096, 61327813, and 61404126).

Ma Liu-Hong^{1, 3}, Han Wei-Hua^{2, 3, †}, Zhao Xiao-Song^{2, 3}, Guo Yang-Yan^{2, 3}, Dou Ya-Mei^{2, 3}, Yang Fu-Hua^{3, 4, ‡}

(color online) Schematic diagrams of the fabrication process for JNTs. (a) The process began with n-type ion implantation in the top silicon layer. (b) Silicon fin and two connected pads were patterned by SEM and ICP etch. (c) A 22-nm thick SiO₂ dielectric layer was grown by thermal oxidation process. (d) A heavily p-doped poly-silicon gate was etched by reactive ion etching. (e) Conventional photolithography and ICP etch with O₂ plasma were employed to pattern the Ohmic contact windows. (f) The control gate electrodes were formed by a 200-nm thick aluminum layer.