Physics-based analysis and simulation model of electromagnetic interference induced soft logic upset in CMOS inverter<xref rid="cpb_27_6_068505_fn1" ref-type="fn">*</xref> <fn id="cpb_27_6_068505_fn1"> <label>*</label> <p>Project supported by the National Natural Science Foundation of China (Grant No. 60776034) and the Open Fund of Key Laboratory of Complex Electromagnetic Environment Science and Technology, China Academy of Engineering Physics (Grant No. 2015-0214.XY.K).</p> </fn>

Physics-based analysis and simulation model of electromagnetic interference induced soft logic upset in CMOS inverter* *

Project supported by the National Natural Science Foundation of China (Grant No. 60776034) and the Open Fund of Key Laboratory of Complex Electromagnetic Environment Science and Technology, China Academy of Engineering Physics (Grant No. 2015-0214.XY.K).

Liu Yu-Qian^{1, †}, Chai Chang-Chun¹, Zhang Yu-Hang², Shi Chun-Lei¹, Liu Yang¹, Fan Qing-Yang¹, Yang Yin-Tang¹

(color online) Schematic diagram of soft logic upset principle through a deviation of the voltage transfer characteristic (VTC) curve.