Near-interface oxide traps in 4H–SiC MOS structures fabricated with and without annealing in NO
Sun Qiu-Jie1, Zhang Yu-Ming1, Song Qing-Wen1, †, Tang Xiao-Yan1, ‡, Zhang Yi-Meng1, Li Cheng-Zhan2, Zhao Yan-Li2, Zhang Yi-Men1
       

(color online) Typical hysteresis C–V loops of N2 POA sample and NO POA sample with different stress times.