Stress-induced leakage current characteristics of PMOS fabricated by a new multi-deposition multi-annealing technique with full gate last process

Wang Yanrong^{1, 2, 3}, Yang Hong^{1, 3}, Xu Hao^{1, 3}, Luo Weichun^{1, 3}, Qi Luwei^{1, 3}, Zhang Shuxiang^{1, 3}, Wang Wenwu^{1, 3, †}, Yan Jiang², Zhu Huilong^{1, 3}, Zhao Chao^{1, 3}, Chen Dapeng^{1, 3}, Ye Tianchun^{1, 3}

(color online) The trap generation rates at the sense voltage (SILC peak) of the four samples.