Analytical capacitance model for 14 nm FinFET considering dual-k spacer
Zheng Fang-Lin, Liu Cheng-Sheng, Ren Jia-Qi, Shi Yan-Ling, Sun Ya-Bin, Li Xiao-Jin
       

(color online) Parasitic capacitance of FinFET with various (a), (b) fin width, (c) spacer thickness, (d) fin height, (e) gate height, (f) fin pitch, and (g) fin number.