Analytical capacitance model for 14 nm FinFET considering dual-k spacer
Zheng Fang-Lin, Liu Cheng-Sheng, Ren Jia-Qi, Shi Yan-Ling, Sun Ya-Bin, Li Xiao-Jin †
       

(color online) (a) Gate fringe capacitance of single-fin FinFET device. (b) Multi-fin structure of FinFET device (N = 2).