(color online) (a) Schematic 3D top-view of the memory FET with the single-layer nanosheet of hexagonal structure, 200-nm-thick ferroelectric P(VDF-TrFE) polymer, and Al gate.^[56] (b) The transfer curve of top-gate-driving single-layer transistor with P(VDF-TrFE) ferroelectric layer; sweep range is from −20 to +20 V and V. Memory hysteresis window of the transistor with 200-nm-thick P(VDF-TrFE) polymer appears to be 14 V. Short pulses of +20 and −20 V on the gate lead to two distinct states of WR and ER, respectively, as shown overlapped with the memory hysteresis curve. from the P(VDF-TrFE) polymer was below 100 pA.^[56] (c) The figure above is the retention properties of WR and ER states recorded under V and V for 1000 s. Inset shows the V 1 s pulse for retention measurements. The following figure is the current dynamics of our memory transistor in response to repetitive input voltage pulses under V. The inset figure shows the periodic pulse mode for WR/read/ER/read process.^[56] (d) Schematics of -PZT FETs device.^[57] (e) Output characteristics of -PZT device. Gate voltage is applied from 0 V to 4 V with a 0.5 V step. Drain voltage is swept from 0 V to 3 V. The inset is P–E curves of a 260-nm-thick PZT under different voltages ranging from −3 to +3 V up to −12 to +12 V at 100 Hz.^[57] (f) The transfer curves of -PZT FET at = 500 mV. Memory window variation with increasing sweep range is shown in the inset.^[57]