Li Wei1, Zheng Zhi2, †, Wang Zhigang3, Li Ping1, Fu Xiaojun2, He Zhengrong2, Liu Fan2, Yang Feng2, Xiang Fan2, Liu Luncai2
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(a) Line
around conventional P channel SOI LDMOS, (b) line
around NPCL P channel SOI LDMOS, (c) electric field around line
in panel (a), and (d) electric field around line
in panel (b).
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