Scaling dependence of memory windows and different carrier charging behaviors in Si nanocrystal nonvolatile memory devices
Yu Jie1, Chen Kun-ji1, †, 
, Ma Zhong-yuan1, Zhang Xin-xin1, Jiang Xiao-fan1, Wu Yang-qing1, Huang Xin-fan1, Oda Shunri2
, Ma Zhong-yuan1, Zhang Xin-xin1, Jiang Xiao-fan1, Wu Yang-qing1, Huang Xin-fan1, Oda Shunri2 The cross-section TEM images of test key cell D along the (a) gate length and (b) width. (c) The high resolution cross-section TEM image of the Si-NC floating gate structure.
