Schematic diagram of all-optical stochastic logic gates and their delay storages in the cascaded VCSELs with optical injection: (a) functional modules; (b) light paths in detail. M-VCSEL, master VCSEL; S-VCSEL, slave VCSEL; IS, isolator; PPLN, periodically poled LiNbO3; μ_M and μ_S, the normalization injection currents of the M-VCSEL and the S-VCSEL, respectively; BS, beam-splitter; PBS, polarization beam-splitter; TEF, transverse electric field; HWP, half wave plate; FR, Faraday rotator; M, mirror; VA, variable attenuator; OA, optical amplifier; the applied electric field E₀ is a digital square wave; the logic outputs X₁ and Y₁ are decoded from the x- and y-polarization with the delay time τ and the scale factor from the PPLN crystal; and the logic outputs X₂ and Y₂ are decoded from the x- and y- polarization emitted by the S-VCSEL.