Modeling of trap-assisted tunneling on performance of charge trapping memory with consideration of trap position and energy level

Lun Zhi-Yuan¹, Li Yun¹, Zhao Kai², Du Gang^{1, †,}, Liu Xiao-Yan¹, Wang Yi¹

TAT current densities under 16-V programming voltage at 1 μs of devices with various peak positions and trap energy levels.