Modeling of trap-assisted tunneling on performance of charge trapping memory with consideration of trap position and energy level
Lun Zhi-Yuan1, Li Yun1, Zhao Kai2, Du Gang1, †, 
, Liu Xiao-Yan1, Wang Yi1
, Liu Xiao-Yan1, Wang Yi1 Schematic illustration of the simulated standard CTM cell with a 4.5/6/10 nm (SiO2/Si3N4/Al2O3) gate stack.
