† Corresponding author. E-mail:

Project supported by the National Natural Science Foundation of China (Grant Nos. 61374150 and 11271146), the State Key Program of the National Natural Science Foundation of China (Grant No. 61134012), the Doctoral Fund of Ministry of Education of China (Grant No. 20130142130012), and the Science and Technology Program of Shenzhen City, China (Grant No. JCYJ20140509162710496).

Recently, it has been demonstrated that memristors can be utilized as logic operations and memory elements. In this paper, we present a novel circuit design for complementary resistive switch (CRS)-based stateful logic operations. The proposed circuit can automatically write the destructive CRS cells back to the original states. In addition, the circuit can be used in massive passive crossbar arrays which can reduce sneak path current greatly. Moreover, the steps for CRS logic operations using our proposed circuit are reduced compared with previous circuit designs. We validate the effectiveness of our scheme through Hspice simulations on the logic circuits.

As it has become increasingly difficult to overcome various physical limits of the traditional CMOS technology,^{[1]} alternative elements are desired for higher performance. An element called memristor (short for “memory resistor”) is a promising candidate. A memristor was first theoretically postulated by Chua in 1971,^{[2]} and later, Williams’s team presented a resistance variable device as a memristor at HP Labs in 2008.^{[3]} Different from other novel nonvolatile random access memories,^{[4,5]} as an emerging nanoscale device, memristor has a lot of advantageous features, such as non-volatility, high density, low power, and good scalability. Recently, researchers have also demonstrated its potential applications in programmable analog circuits,^{[6–8]} chaotic oscillator circuits,^{[9–11]} and neural networks.^{[12]}

In addition, a memristor can be used in logic circuits,^{[13–15]} logic arrays,^{[16–18]} and other structures like CMOS-memristor hybrids.^{[19]} Over the years, the memristor has been proposed as a replacement for the current CMOS-based memory architectures. For example, memristor-based crossbar arrays were used as feasible nonvolatile random access memories (RAMs) in Ref. [20]. However, passive crossbar arrays have the common problem about sneak path current due to interference from the neighboring cells when selecting a designated cell within the arrays.^{[21–23]} Recently, the complementary resistive switch (CRS), which consists of two bipolar memristive elements anti-serially, was proposed to overcome the disadvantage of sneak path.^{[24]} The element, including a high resistance state and a low resistance state, is used to encode either logic 0, 1, or ON state (see Fig. *X* is in the high resistance state (HRS), and memristive element *Y* is in the low resistance state (LRS), then CRS is in state 0. If memristive element *X* is in the LRS, and memristive element *Y* is in the HRS, then CRS is in state 1. If memristive elements *X* and *Y* are both in the LRS, then the CRS is in state ON. The transitions between these states depend on the applied biasing voltage across the CRS, controlled by *V*_{th1}, *V*_{th2}, *V*_{th3}, and *V*_{th4} threshold voltages.^{[24]}

Since Linn *et al.* proposed the CRS architecture in Ref. [24], many scholars have paid much attention to the CRS. In Ref. [15], Yang *et al.* proposed a scheme to implement the CRS-based stateful logic operations using material implication (IMP). However, during the IMP operation, the state 1 stored in the CRS_{P} was reset to state 0, and for the NAND operation, the state 1 stored in the CRS_{P1} and CRS_{P2} was similarly reset to state 0. This scheme for the stateful logic operations partially destructs the original states stored in the input CRS cells. Moreover, the CRSs used in input and output cells are two different types of elements, then the configuration and parameter of input cell (CRS_{P}) and output cell (CRS_{Q}) are completely different. The output cell CRS_{Q} can be only used as an output cell, which cannot be used as an input cell to perform the next logic operation, so it is hardly applied to massive passive crossbar arrays. In order to solve these issues, we put forward a circuit which consists of two parts including two CMOS switches, a resistor, and two voltage comparators. The circuit can be highly compatible with the CRS, and can be integrated to the peripheral circuit. The circuit will not bring extra area consumption of storage cells in massive passive crossbar arrays either. The main contributions of this paper are as follows.

The remainder of this paper is organized as follows. Section 2 presents our proposed circuit for CRS IMP, NAND operations and the CRS-based crossbar architecture with our proposed circuit. In Section 3, simulation results are provided to demonstrate the effectiveness and superior performance of the proposed circuit. Section 4 concludes this paper.

In this section, at first, we describe the CRS IMP operation using the proposed circuit. On this basis, we propose the CRS NAND operation. In order to apply CRS-based logic operations to crossbar arrays, we choose the same type of CRS as the CRS_{P} and CRS_{Q}. By implementing the two stateful logic operations, we show that our proposed circuit can perfectly address these problems existing in Ref. [15].

To perform the CRS IMP operation using our proposed circuit, we consider the basic structure shown in Fig.

The circuits of red dashed line and blue dashed line present our proposed circuit. In the circuit of red dashed line, we adopt two CMOS switches S_{1} and S_{2}, a voltage comparator C_{1}, and a resistor *R*_{S} of which resistance is fairly small compared with the resistance of CRS_{P} state ON (*R*_{CRSONP}). In the circuit of the blue dashed line, we only use a voltage comparator C_{2} to implement the related functions. In order to perform the CRS IMP operation using our proposed circuit, voltage *V*_{ONCRSP–0} and *V*_{CLEARP} are applied to switch S_{1} and S_{2}. Voltage *V*_{ONCRSP–0} is negative which can only switch CRS_{P} from state 0 to state ON, and voltage *V*_{CLEARP} is positive which resets CRS_{P} to state 0. The output voltage of C_{1}, namely *V*_{OUT1}, is used to select switch S_{1} or S_{2}. The S_{1} is a PMOS switch, and the S_{2} is a NMOS switch. When voltage *V*_{OUT1} is negative, switch S_{1} is turned on, S_{2} is turned off, and voltage *V*_{ONCRSP–0} is applied to CRS_{P}, resistor *R*_{S} and *R*_{G}. When voltage *V*_{OUT1} is positive, switch S_{2} is turned on, S_{1} is turned off, and voltage *V*_{CLEARP} is applied to the circuit. Now, we show how the circuit in Fig. *V*_{POS1} (positive terminal of C_{1}) is equal to zero. We apply a positive pulse to voltage *V*_{REF1}, and thus voltage *V*_{OUT1} will be negative, which turns on switch S_{1}, imposes voltage *V*_{ONCRSP–0} to the circuit. Under voltage *V*_{ONCRSP–0}, CRS_{P} either stays in state 1 or switches from state 0 to state ON. The magnitude of the current passing through *R*_{S}, CRS_{P}, and *R*_{G} when CRS_{P} is in state ON is larger than the one when CRS_{P} is in state 0. In order to perform CRS IMP operation correctly, the relationships of various operation voltages are given in Eqs. (_{P} is in state ON, we define the potential of the node B (see Fig. *V*_{ONPOS1}, and we define the potential of the node A as *V*_{GON}. When CRS_{P} is in state 1, we define the potential of the node B as *V*_{1POS1}, and we define the potential of the node A as *V*_{G1}. Obviously, voltage *V*_{GON} and *V*_{G1} meet Eq. (*R*_{S} when CRS_{P} is in state ON is much larger than the one when CRS_{P} is in state 1. That is to say, voltage *V*_{1POS1} with CRS_{P} staying in state 1 is less than *V*_{ONPOS1} with CRS_{P} staying in state ON, so voltage *V*_{1POS1} and *V*_{ONPOS1} meet Eq. (*V*_{REF1} and *V*_{REF2}. Here, the proposed circuit is designed by using the parameters listed in Section 3. The voltages including *V*_{ONPOS1}, *V*_{1POS1}, *V*_{G1}, and *V*_{GON} are measured in the circuit simulation, and the reference voltages, namely *V*_{REF1} and *V*_{REF2}, are the added voltages.

*V*

_{Pth2},

*V*

_{Pth3}, and

*V*

_{Pth4}are the threshold voltages of CRS

_{P},

*V*

_{Qth4}is the threshold voltage of CRS

_{Q},

*V*

_{1POS1},

*V*

_{ONPOS1},

*V*

_{GON}, and

*V*

_{G1}are all negative voltage. As shown in Fig.

*V*

_{REF1}is a positive voltage, and

*R*

_{REF2}is negative which is larger than

*V*

_{GON}and less than

*V*

_{G1}. In Step 2, voltage

*V*

_{REF1}is negative, which is larger than

*V*

_{1POS1}and less than

*V*

_{ONPOS1}; and voltage

*R*

_{REF2}is also negative which is less than

*V*

_{GON}and

*V*

_{G1}. Now, we analyze the four input cases and the operation process.

_{P} is in state 0, CRS_{Q} is also in state 0. As shown in Fig. *V*_{REF1} is larger than *V*_{POS1} which is about 0, and *V*_{OUT1} is negative which turns on S_{1}. Then *V*_{ONCRSP–0} is applied to the circuit (shown in Fig. *V*_{ONCRSP–0}, CRS_{P} will be changed to state ON, then voltage *V*_{POS2} is equal to *V*_{GON} which is smaller than *V*_{REF2} (see Fig. *V*_{OUT2} will be a negative voltage which is defined as *V*_{SETQ}, and voltage *V*_{SETQ} will set CRS_{Q} to state 1. Secondly, when CRS_{P} switches to state ON, *V*_{REF1} will be less than *V*_{ONPOS1}. In this way, switch S_{2} is turned on, and voltage *V*_{CLEARP} will be applied to the circuit. Under voltage *V*_{CLEARP}, CRS_{P} will be changed from state ON to state 0. Note that voltage *V*_{CLEARP} is positive. As a result, *V*_{POS1} is also positive, switch S_{2} will be always turned on. *V*_{RG} will be a small positive voltage, at the moment, we will apply a negative voltage to *V*_{REF2} (see Fig. *V*_{OUT2} will be a positive voltage which we define *V*_{LOW}. Voltage *V*_{LOW} is less than *V*_{Qth1}, which does not change the state of CRS_{Q}, here, *V*_{Qth1} is the threshold voltage of CRS_{Q}, then CRS_{Q} will still stay in state 1. After that, CRS_{P} is in state 0, and CRS_{Q} is changed to state 1.

_{P} is in state 0, CRS_{Q} is in state 1. Like Case 1, under *V*_{ONCRSP–0}, CRS_{P} will be changed to state ON, then under voltage *V*_{CLEARP}, CRS_{P} will return to its original state (state 0). At the same time, CRS_{Q} will not be changed. After that, CRS_{P} is in state 0, CRS_{Q} is in state 1.

_{P} is in state 1, CRS_{Q} is in state 0. Firstly, under voltage *V*_{ONCRSP–0}, CRS_{P} remains in state 1, then voltage *V*_{POS2} is equal to *V*_{G1} which is larger than *V*_{REF2}, *V*_{OUT2} will not be equal to voltage *V*_{LOW} which will not change the state of CRS_{Q}. Secondly, when CRS_{P} is in state 1 under voltage *V*_{ONCRSP–0}, *V*_{POS1} is equal to *V*_{1POS1} which is less than voltage *V*_{REF1}. Then *V*_{OUT1} is still negative, and switch S_{2} will not be turned on. In this way, voltage *V*_{POS2} is still equal to *V*_{G1}, which is still larger than *V*_{REF2}. So, *V*_{OUT2} will still be equal to voltage *V*_{LOW} which will not change the state of CRS_{Q}. After that, CRS_{P} is in state 1, CRS_{Q} is in state 0.

_{P} is in state 1, CRS_{Q} is also in state 1. Like Case 3, under *V*_{ONCRSP–0}, CRS_{P} remains in state 1. At the same time, CRS_{Q} will not be changed. After that, CRS_{P} is in state 1, CRS_{Q} is in state 1.

The CRS IMP operation can be implemented using the proposed circuit during two steps. Table

According to Ref. [13], any logic operation can be implemented using NAND gates. Hence, the following section will illustrate the details of CRS NAND operation. The two inputs NAND operation needs three CRS cells, CRS_{P1}, CRS_{P2} (NAND inputs), and CRS_{Q} which will store the result after NAND operation. Figure

Like the CRS IMP operation, the circuits of red dashed line and green dashed line are added to CRS_{P1} and CRS_{P2} respectively, and the circuit of blue dashed line is used to drive CRS_{Q}. The configuration and parameter in the circuits of red dashed line and green dashed line are completely the same. In order to describe the CRS NAND operation, we make some definitions. When CRS_{P1} is in state ON under voltage *V*_{ONCRSP–0}, we define the potential of the node B as *V*_{ONPOS1} (see Fig. _{P1} is still in state 1 under voltage *V*_{ONCRSP–0}, we define the potential of the node B as *V*_{1POS1}. Similarly, we can define *V*_{ONPOS2} and *V*_{1POS2}. When CRS_{P1} and CRS_{P2} are both in state 1 under voltage *V*_{ONCRSP–0}, we define the potential of the node A as *V*_{1–1POS3}. When one of CRS_{P1} and CRS_{P2} is in state ON and the other is in state 1 under voltage *V*_{ONCRSP–0}, we define the potential of the node A as *V*_{1–ONPOS3}. When CRS_{P1} and CRS_{P2} are both in state ON under voltage *V*_{ONCRSP–0}, we define the potential of the node A as *V*_{ON–ONPOS3}. Apparently, equations (*V*_{REF1}, *V*_{REF2}, and *V*_{REF3}. Here, like the CRS IMP operation, the proposed circuit is also designed by using the parameters listed in Section 3. The voltages including *V*_{ONPOS1}, *V*_{1POS1}, *V*_{ONPOS2}, *V*_{1POS2}, *V*_{1–1POS3}, *V*_{1–ONPOS3}, and *V*_{ON–ONPOS3} are measured in the circuit simulation, and the reference voltages, namely *V*_{REF1}, *V*_{REF2}, and *V*_{REF3} are the added voltages.

*V*

_{Qth2}is the threshold voltage of CRS

_{Q}, voltage

*V*

_{ONPOS1},

*V*

_{ONPOS2}, and

*V*

_{1–1POS3}are all negative. To implement the CRS NAND operation, in Step 1, we apply voltage

*V*

_{SETQ}to CRS

_{Q}, which sets CRS

_{Q}to state 1 unconditionally. Then we remove voltage

*V*

_{SETQ}. Considering Fig.

*V*

_{POS1}and

*V*

_{POS2}are about 0, we apply a positive voltage to

*V*

_{REF1}and

*V*

_{REF2}, then

*V*

_{OUT1}and

*V*

_{OUT2}are negative and will turn on switch S

_{1}and S

_{3}, so voltage

*V*

_{ONCRSP–0}will be added to the circuit. At the same time, a negative voltage is applied to

*V*

_{REF3}which is larger than

*V*

_{1–ONPOS3},

*V*

_{ON–ONPOS3}, and less than

*V*

_{1–1POS3}. In Step 3, we apply a negative voltage to

*V*

_{REF1}which is larger than

*V*

_{1POS1}and less than

*V*

_{ONPOS1}, and it is the same as voltage

*V*

_{REF2}. In the meantime, a positive voltage is applied to

*V*

_{REF3}which is larger than

*V*

_{POS3}. Now, we analyze the four input cases and the operation process.

_{P1} is in state 0, and CRS_{P2} is also in state 0. Firstly, voltage *V*_{SETQ} sets CRS_{Q} state 1, then voltage *V*_{ONCRSP–0} is added to the circuit, CRS_{P1} and CRS_{P2} will be changed to state ON under voltage *V*_{ONCRSP–0}. At the same time, the added voltage *V*_{REF3} is larger than *V*_{ON–ONPOS3}, then voltage *V*_{OUT3} is a negative voltage which we define as *V*_{QLOW}. The magnitude of *V*_{QLOW} is less than *V*_{Qth3}, which will not change the state of CRS_{Q}, here, *V*_{Qth3} is the threshold voltage of CRS_{Q}. Secondly, the added negative voltage *V*_{REF1} and *V*_{REF2} are less than *V*_{ONPOS1} and *V*_{ONPOS2}, respectively. So, voltage *V*_{OUT1} and *V*_{OUT2} are positive which will turn on switch S_{2} and S_{4}, voltage *V*_{CLEARP} is added to the circuit. Under voltage *V*_{CLEARP}, CRS_{P1} and CRS_{P2} will be reset to state 0, and voltage *V*_{POS1} and *V*_{POS2} will be positive which are larger than *V*_{REF1} and *V*_{REF2} respectively, switch S_{1} and S_{3} will not be always turned on, therefore CRS_{P1} and CRS_{P2} will remain in state 0. However, biased by voltage *V*_{CLEARP}, *V*_{POS3} is a small positive voltage. So we apply an appropriate positive voltage to *V*_{REF3} which is larger than *V*_{POS3}, the voltage *V*_{OUT3} is equal to *V*_{QLOW} which will not change the state of CRS_{Q}. In this way, CRS_{Q} is still in state 1. After that, CRS_{P1} is in state 0, CRS_{P2} is in state 0, and CRS_{Q} is in state 1.

_{P1} is in state 0, CRS_{P2} is in state 1. Firstly, voltage *V*_{SETQ} sets CRS_{Q} state 1, then voltage *V*_{ONCRSP–0} is added to the circuit. Under voltage *V*_{ONCRSP–0}, CRS_{P1} will switch to state ON, while CRS_{P2} keeps the state. Voltage *V*_{POS3} is *V*_{1–ONPOS3}, while the added voltage *V*_{REF3} is larger than *V*_{1–ONPOS3}, so voltage *V*_{OUT3} is equal to *V*_{QLOW} which will not change the state of CRS_{Q}. Secondly, the added negative voltage *V*_{REF1} is less than *V*_{ONPOS1}, then switch S_{2} will be turned on, so CRS_{P1} will be reset to state 0 biased by voltage *V*_{CLEARP}. For the fact that the added negative voltage *V*_{REF2} is larger than *V*_{1POS2}, then switch S_{4} will not be turned on, so the state of CRS_{P2} will not be changed. While biased by voltage *V*_{ONCRSP–0} and *V*_{CLEARP}, *V*_{POS3} is a small positive voltage. Like Case 1, we apply the same voltage to *V*_{REF3} which is larger than *V*_{POS3}. In this way, CRS_{Q} is still in state 1. After that, CRS_{P1} is in state 0, CRS_{P2} is in state 1, and CRS_{Q} is in state 1.

_{P1} is in state 1, CRS_{P2} is in state 0. Case 3 is the same as Case 2. After that, CRS_{P1} is in state 1, CRS_{P2} is in state 0, and CRS_{Q} is in state 1.

_{P1} is in state 1, CRS_{P2} is also in state 1. Firstly, voltage *V*_{SETQ} sets CRS_{Q} to state 1, then voltage *V*_{ONCRSP–0} is added to the circuit. Under voltage *V*_{ONCRSP–0}, CRS_{P1} and CRS_{P2} will keep the state. In the meantime, voltage *V*_{POS3} is equal to *V*_{1–1POS3}, and voltage *V*_{REF3} is less than *V*_{1–1POS3} (shown in Fig. _{3} output a positive voltage. Here, we define the positive voltage *V*_{CLEARQ}, which can reset CRS_{Q} to state 0. Secondly, the added negative voltage *V*_{REF1} and *V*_{REF2} are larger than *V*_{1POS1} and *V*_{1POS2}, respectively. So, voltage *V*_{OUT1} and *V*_{OUT2} are negative which will not turn on switch S_{2} and S_{4}, and voltage *V*_{CLEARP} will not be added to the circuit. At the same time, the added positive voltage *V*_{REF3} is larger than *V*_{1–1POS3}. The voltage *V*_{OUT3} is equal to *V*_{QLOW} which will not change the state of CRS_{Q}. After that, CRS_{P1} is in state 1, CRS_{P2} is in state 1, and CRS_{Q} is in state 0.

The CRS NAND operation can be implemented using the proposed circuit during three steps. Table

To perform *N* inputs CRS NAND operation, we need *N* + 1 CRS cells to achieve the function, in which *N* CRS cells are used for *N* inputs cells, and the other is considered as the output cell. It needs only three steps. In Step 1, CRS_{Q} is initialized to state 1, then *N* inputs CRS NAND operation can be executed by two steps using our proposed circuit. For the CRS NAND operation in Ref. [10], it needs four steps. For memristor NAND operation in the previous literature, it needs N times IMP, so N inputs memristor NAND operation requires *N* + 1 steps (N IMP steps plus one initialization). The comparison about steps of IMP and NAND operations is shown in Table

In the preliminary, we have already implemented the two foremost CRS logic operations. According to Ref. [13], any logic operation can be performed using the NAND gates. In addition, other stateful logic operations can be also implemented using our proposed circuit. We will apply the CRS NAND operation with our proposed circuit to crossbar architecture. Figure

The following presents the simulation results of CRS IMP and NAND operations using Hspice simulation tool. To perform the CRS stateful logic operations, the parameters of CRS cells should satisfy Eqs. (_{P} and CRS_{Q}, we choose *R*_{ON} = 100 Ω for state ON of memristive elements *X* and *Y*, and *R*_{OFF} = 10 kΩ for state OFF of memristive elements *X* and *Y*. In this way, we can ensure the same configuration and parameter of CRS_{P} and CRS_{Q}, which can be applied to massive crossbar arrays better. Moreover, we select *R*_{G} = 50 Ω and *R*_{S} = 20 Ω. We use −12 V for *V*_{SETQ}, 12 V for *V*_{CLEARP} and *V*_{CLEARQ}. According to Eq. (*V*_{ONCRSP–0} is −8 V.

Figure _{P} and CRS_{Q} are represented by two memristive elements which are called state PX, state QX (blue bold line) and state PY, state QY (green bold line), respectively. As shown in Fig. _{P} and CRS_{Q}. The first state is the original state. After Step 1, CRS_{P} and CRS_{Q} switch to the second state, and after Step 2, CRS_{P} and CRS_{Q} switch to the third state. Now, we take Case 1 for example. The original states of CRS_{P} and CRS_{Q} are state 0. After Step 1, CRS_{P} switches to state ON, while CRS_{Q} switches to state 1. After Step 2, CRS_{P} switches to state 0, while CRS_{Q} remains unchanged. After that, the state of CRS_{Q} is the result of IMP operation, and CRS_{P} remains in its original state, which is not destroyed. It is the same as the other three cases (see Fig.

Figure _{P1}, CRS_{P2}, and CRS_{Q} (see Fig. _{P1} and CRS_{P2} are the original states, and the first state of CRS_{Q} is the initialized state. During Step 1, CRS_{Q} is initialized to state 1. After Step 2, CRS_{P1}, CRS_{P2}, and CRS_{Q} switch to the second state, and after Step 3, CRS_{P1}, CRS_{P2}, and CRS_{Q} switch to the third state. Now, we take Case 1 for example. The original states of CRS_{P1} and CRS_{P2} are state 0. During Step 1, CRS_{Q} is initialized to state 1. After Step 2, CRS_{P1} and CRS_{P2} both switch to state ON, and CRS_{Q} remains in state 1. After Step 3, CRS_{P1} and CRS_{P2} both switch from state ON to state 0, and CRS_{Q} still remains in state 1. After that, the state of CRS_{Q} is the result of NAND operation, CRS_{P1} and CRS_{P2} remain in their original states, which are not destroyed. It is the same as the other three cases (see Fig.

In this paper, we present a circuit design for CRS-based stateful logic operations. Here, we describe CRS IMP and NAND operations using our proposed circuit in detail. We only need two steps to implement the CRS IMP operation compared with the previous CRS IMP operation in Ref. [15]. Furthermore, only three steps are required for implementing N inputs NAND gate, whereas memristor based NAND operation needs *N* + 1 steps. The most important feature of our proposed circuit is that the states stored in input cells will not be damaged. In the end, due to the fact that we use the same type of CRS as input and output cells, we can apply the circuit to massive passive crossbar arrays.

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