Wu Chen-Fei 1, 2, Chen Yun-Feng 1, 2, Lu Hai 1, 2, †, , Huang Xiao-Ming 3, Ren Fang-Fang 1, 2, Chen Dun-Jun 1, 2, Zhang Rong 1, 2, Zheng You-Dou 1, 2
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(a1) and (a2) Surface potential VSP profiles near the edge of electrodes of the a-IGZO TFT. The shaded regions depict the topographic edges of the S/D electrodes. The voltage drops at drain and source contacts are highlighted. (b) Channel, source, and drain resistance as a function of gate bias voltage of the TFT. |