Ultra-low specific on-resistance high-voltage vertical double diffusion metal–oxide–semiconductor field-effect transistor with continuous electron accumulation layer
Ma Da1, Luo Xiao-Rong1, 2, †, 
, Wei Jie1, Tan Qiao1, Zhou Kun1, Wu Jun-Feng1
, Wei Jie1, Tan Qiao1, Zhou Kun1, Wu Jun-Feng1 Key steps to prepare the CEA-VDMOS: (a) etch a deep trench and form a thin oxide layer, (b) selectively etch the bottom oxide, (c) fill the trench with the p-type silicon, (d) implant arsenic to form N+ region, (e) form the P-pillar, (f) form source/gate contact regions and electrodes and back-etch forming the drain electrode.
