An ultra-low specific on-resistance trench LDMOS with a U-shaped gate and accumulation layer<xref ref-type="fn" rid="cpb141415fn1">*</xref>

An ultra-low specific on-resistance trench LDMOS with a U-shaped gate and accumulation layer*

Li Peng-Cheng, Xiao-Rong Luo†, Luo Yin-Chun, Zhou Kun, Shi Xian-Long, Zhang Yan-Hui, Lv Meng-Shan

(a) Electric field and potential distributions under drain and source. (b) Electric fields of the BOX layer at breakdown with different values of T _ox ( x = 14.0 μm).