An ultra-low specific on-resistance trench LDMOS with a U-shaped gate and accumulation layer<xref ref-type="fn" rid="cpb141415fn1">*</xref>

An ultra-low specific on-resistance trench LDMOS with a U-shaped gate and accumulation layer*

Li Peng-Cheng, Xiao-Rong Luo†, Luo Yin-Chun, Zhou Kun, Shi Xian-Long, Zhang Yan-Hui, Lv Meng-Shan

(a) Electric field distributions around the trench for UG LDMOS and CT LDMOS. (b) Horizontal electric field distributions at the surface ( y = 0.6 μm) and bulk ( y = 10.0 μm) of the trench in UG LDMOS and CT LDMOS.