An ultra-low specific on-resistance trench LDMOS with a U-shaped gate and accumulation layer<xref ref-type="fn" rid="cpb141415fn1">*</xref>

An ultra-low specific on-resistance trench LDMOS with a U-shaped gate and accumulation layer*

Li Peng-Cheng, Xiao-Rong Luo†, Luo Yin-Chun, Zhou Kun, Shi Xian-Long, Zhang Yan-Hui, Lv Meng-Shan

Equi-potential contours at breakdown voltage for (a) UG LDMOS (662 V) and (b) CT LDMOS (351 V).