An ultra-low specific on-resistance trench LDMOS with a U-shaped gate and accumulation layer*
Li Peng-Cheng, Xiao-Rong Luo†, Luo Yin-Chun, Zhou Kun, Shi Xian-Long, Zhang Yan-Hui, Lv Meng-Shan
       
(a) Schematic cross-sectional view of the UG LDMOS. (b) Working mechanism of the gate structure in on-state. (c) Charges distribution in the off-state.