Mechanism of single-event transient pulse quenching between dummy gate isolated logic nodes<xref ref-type="fn" rid="cpb140521">*</xref>

Mechanism of single-event transient pulse quenching between dummy gate isolated logic nodes*

Chen Jian-Jun†, Chi Ya-Qing, Liang Bin

Fig.#cod#x00A0;1. Four different layout placements for adjacent PMOS circuits in adjacent inverters: a layout 1, b layout 2, c layout 3, d layout 4.