Hybrid phase-locked loop with fast locking time and low spur in a 0.18-μm CMOS process
朱思衡, 司黎明, 郭超, 史君宇, 朱卫仁
Hybrid phase-locked loop with fast locking time and low spur in a 0.18-μm CMOS process
Zhu Si-Heng (朱思衡), Si Li-Ming (司黎明), Guo Chao (郭超), Shi Jun-Yu (史君宇), Zhu Wei-Ren (朱卫仁)
Chin. Phys. B . 2014, (7): 78401 -078401 .  DOI: 10.1088/1674-1056/23/7/078401