中国物理B ›› 2008, Vol. 17 ›› Issue (10): 3565-3573.doi: 10.1088/1674-1056/17/10/007

• GENERAL • 上一篇    下一篇

Planar ion chip design for scalable quantum information processing

万金银, 王育竹, 刘 亮   

  1. Key Laboratory for Quantum Optics, Shanghai Institute of Optics and Fine Mechanics, Chinese Academy of Sciences, Shanghai 201800, China
  • 收稿日期:2008-02-27 修回日期:2008-03-24 出版日期:2008-10-20 发布日期:2008-10-20
  • 基金资助:
    Project supported by the Shanghai Pujiang Programme and the National Basic Research Programme of China (Grant No 2006CB921202).

Planar ion chip design for scalable quantum information processing

Wan Jin-Yin(万金银), Wang Yu-Zhu(王育竹), and Liu Liang(刘亮)†   

  1. Key Laboratory for Quantum Optics, Shanghai Institute of Optics and Fine Mechanics, Chinese Academy of Sciences, Shanghai 201800, China
  • Received:2008-02-27 Revised:2008-03-24 Online:2008-10-20 Published:2008-10-20
  • Supported by:
    Project supported by the Shanghai Pujiang Programme and the National Basic Research Programme of China (Grant No 2006CB921202).

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摘要： We investigate a planar ion chip design with a two-dimensional array of linear ion traps for scalable quantum information processing. Qubits are formed from the internal electronic states of trapped $^{40}$Ca$^{+}$ ions. The segmented electrodes reside in a single plane on a substrate and a grounded metal plate separately, a combination of appropriate rf and DC potentials is applied to them for stable ion confinement. Every two adjacent electrodes can generate a linear ion trap in and between the electrodes above the chip at a distance dependent on the geometrical scale and other considerations. The potential distributions are calculated by using a static electric field qualitatively. This architecture provides a conceptually simple avenue to achieving the microfabrication and large-scale quantum computation based on the arrays of trapped ions.

Abstract: We investigate a planar ion chip design with a two-dimensional array of linear ion traps for scalable quantum information processing. Qubits are formed from the internal electronic states of trapped $^{40}$Ca$^{+}$ ions. The segmented electrodes reside in a single plane on a substrate and a grounded metal plate separately, a combination of appropriate rf and DC potentials is applied to them for stable ion confinement. Every two adjacent electrodes can generate a linear ion trap in and between the electrodes above the chip at a distance dependent on the geometrical scale and other considerations. The potential distributions are calculated by using a static electric field qualitatively. This architecture provides a conceptually simple avenue to achieving the microfabrication and large-scale quantum computation based on the arrays of trapped ions.

Key words: ion traps, ion chip, quantum information processing

中图分类号:  (Atomic and molecular beam sources and techniques)

  • 37.20.+j
03.67.Lx (Quantum computation architectures and implementations)