Contact resistance asymmetry of amorphous indium–gallium–zinc–oxide thin-film transistors by scanning Kelvin probe microscopy
Wu Chen-Fei1, 2, Chen Yun-Feng1, 2, Lu Hai1, 2, †, , Huang Xiao-Ming3, Ren Fang-Fang1, 2, Chen Dun-Jun1, 2, Zhang Rong1, 2, Zheng You-Dou1, 2
Jiangsu Provincial Key Laboratory of Advanced Photonic and Electronic Materials, and School of Electronic Science and Engineering, Nanjing University, Nanjing 210093, China
Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210093, China
Peter Grünberg Research Center, Nanjing University of Posts and Telecommunications, Nanjing 210003, China

 

† Corresponding author. E-mail: hailu@nju.edu.cn

Project supported by the Key Industrial R&D Program of Jiangsu Province, China (Grant No. BE2015155), the Priority Academic Program Development of Higher Education Institutions of Jiangsu Province, China, and the Fundamental Research Funds for the Central Universities, China (Grant No. 021014380033).

Abstract
Abstract

In this work, a method based on scanning Kelvin probe microscopy is proposed to separately extract source/drain (S/D) series resistance in operating amorphous indium–gallium–zinc–oxide (a-IGZO) thin-film transistors. The asymmetry behavior of S/D contact resistance is deduced and the underlying physics is discussed. The present results suggest that the asymmetry of S/D contact resistance is caused by the difference in bias conditions of the Schottky-like junction at the contact interface induced by the parasitic reaction between contact metal and a-IGZO. The overall contact resistance should be determined by both the bulk channel resistance of the contact region and the interface properties of the metal-semiconductor junction.

1. Introduction

Amorphous indium–gallium–zinc–oxide thin-film transistors (a-IGZO TFTs) have been widely studied as prospective devices for next generation display applications due to high carrier mobility, low off-state leakage, low processing temperature, and good uniformity compared with conventional silicon-based TFTs.[14] Due to the rapidly increasing demand for ultra-high resolution displays, scaling in a-IGZO TFTs is inevitable. In this case, the contact property between the source/drain electrodes and the a-IGZO channel plays an important role in the overall electrical performance of the TFTs, as the series contact resistance would become comparable to the channel resistance (RCH) for short channel devices. In order to accurately model the contact properties of the TFTs, analysis of the total series contact resistance is no longer enough. It is necessary to separately extract the source and drain resistances (RS and RD), considering the asymmetric nature of RS and RD due to the difference in bias conditions and fabrication process variations. Until recently, only a few results have been reported on separate extraction of RS and RD in a-IGZO TFTs.[5,6] Moreover, the validity of the extraction methods employed in those studies mostly relies on the accuracy of the equivalent circuit model used, while the underlying physics of contact asymmetry is less studied.

In this paper, the contact properties of a-IGZO TFTs is studied by imaging the potential profile of the TFT channel by using scanning Kelvin probe microscopy (SKPM). In this manner, RS, RD, and RCH of an operating TFT at a series of bias conditions are extracted. The underlying physics of the asymmetric nature of source and drain contact resistance is discussed.

2. Experiment

Figure 1 illustrates the schematic diagram of the SKPM setup with the a-IGZO TFT under test. The inverted-staggered a-IGZO TFT is fabricated on heavily doped Si substrate, which is also served as bottom gate. A 40-nm a-IGZO active layer is deposited by dc sputtering on a 200-nm PECVD SiOx gate insulator. The active region of the TFT is then defined by photolithography and wet chemical etching. Next, Au/Ti (40 nm/10 nm) stacked S/D electrodes are deposited by e-beam evaporation and defined by the lift-off technique. Finally, the whole device is thermally annealed at 200 °C in air. The channel width (W) and length (L) of the measured TFT are 200 μm and 10 μm, respectively. The TFT works in enhancement mode with a sub-threshold swing of 0.23 V/dec, threshold voltage (Vth, the gate to source voltage where normalized drain current LIDS/W reaches 1 nA) of 1.98 V and field effective mobility of 6.80 cm2·V−1·s−1.

The SKPM measurement is conducted using the surface potential mapping mode of an atomic force microscope (AFM) with a Pt-coated tip (diameter= 30 nm). The topography of the sample is measured under conventional non-contact mode with a working frequency of ωm, which is approximately equal to the resonance frequency of the cantilever, while the synchronous measurement of the surface potential is realized by applying an additional alternative voltage VDC+VAC sin(ωet) (ωe < ωm) to the tip. The electrostatic force between the tip and the sample can be expressed as[7]

where C is the sample-to-tip capacitance, Z is the sample-to-tip distance, and VSP is the sample potential. Thus, the value of VSP can be obtained by choosing a proper VDC such that the amplitude of the ωe component of Fe (corresponds to the output signal of a lock-in amplifier at ωe) is nullified. In this way, the surface potential can be represented by the corresponding value of VDC.[8] The measured surface potential profile should reflect the transport properties of the TFT. Various studies have shown that the back channel surface potential of oxide and organic TFTs closely follow the potential in the accumulation layer for the non-pinched-off conduction region of the channel.[911] Simulation results also confirm that the back channel potential follows the potential contour across the channel with a thickness of 40 nm.[12]

Fig. 1. Schematic diagram of the SKPM setup and the a-IGZO TFT under test.

In order to analyze the contact properties of the TFT at different working conditions, the surface potential across one certain section line along the TFT channel is measured repeatedly under a series of gate biases (VGS). The TFT under test is biased by using a Keithley sourcemeter, which also records drain current (IDS) of the TFT during the SKPM measurement. Under each gate bias, the surface potential measurement is repeated three times to confirm the repeatability. It is also worth noting that the back channel of the a-IGZO TFT is exposed to air during the SKPM measurement, which may introduce measurement errors due to the environment-related degradation effect of the TFT. To solve this, the transfer characteristics of the TFT are measured directly before and after the SKPM measurement. The field-effect mobility and sub-threshold swing of the TFT show no change, while the shift of threshold voltage is less than 0.5 V, indicating that environmental effect is negligible for this study.

3. Results and discussion

Figure 2(a) shows the lateral topography of the TFT measured by AFM. The actual channel length and the S/D electrode thickness are 9.21 μm and 53 nm, respectively. Figure 2(b) shows a series of surface potential profiles along the TFT channel measured at different gate biases with a fixed drain voltage (VDS) of 5 V. The shaded regions illustrate the topographic edges of the S/D electrodes. In order to eliminate the impact of channel-electrode work function difference and facilitate surface potential analysis, the potential profile measured at VGS = VDS = 0 V has been subtracted from all measured potential profiles of the operating TFT. It is clear that the potential profiles highlight the importance of contact resistance in the transport process of a working TFT, as a sharp potential drop is observed at the edge of source electrode when the TFT is turned on (VGS>Vth). As mentioned before, the surface potential of the channel follows the potential contour of the whole channel when the TFT operates in the non-saturation region (VGSVth>VDS), which means that the cross section of the active layer along the width of the channel at any position x is an equipotential surface. As a result, the S/D resistance RS and RD of the TFT operating in the non-saturation region can be calculated by dividing the voltage drop at S/D contacts (see Figs. 3(a1) and 3(a2)) by IDS for each gate bias, i.e., RS,D = ΔVS,D/IDS, which is also known as the “microscopic contact resistance”.[13,14] The channel resistance is then derived as RCH = VDS/IDSRSRD.

Fig. 2. (a) Surface topography of the a-IGZO TFT along the channel length. (b) Surface potential profiles of the a-IGZO TFT with VDS = 5 V and VGS increases from 1 V to 15 V (each profile curve is sequentially offset by 1 V for clarity). The shaded regions depict the topographic edges of the S/D electrodes. The lines in blue indicate the potential profiles for TFTs working in the non-saturation region (VGSVth>VDS) while the lines in orange indicate the potential profiles for TFTs working in the saturation region (VGSVthVDS).
Fig. 3. (a1) and (a2) Surface potential VSP profiles near the edge of electrodes of the a-IGZO TFT. The shaded regions depict the topographic edges of the S/D electrodes. The voltage drops at drain and source contacts are highlighted. (b) Channel, source, and drain resistance as a function of gate bias voltage of the TFT.

The gate bias dependence of RCH, RS, and RD is illustrated in Fig. 3(b). It is clear that RCH decreases with increasing VGS. That is, by applying a larger VGS, the gate-voltage-induced carrier concentration in the TFT channel increases and the active layer becomes more conductive. The variation of RS and RD as a function of VGS follows the same trend, which is typical for bottom-gate a-IGZO TFTs.[15] It is also clear that RS is always larger than RD for all applied gate biases. Device processing related structural asymmetry is firstly examined as a possible cause of this S/D contact asymmetry. The surface potential is measured in the same way with exchanged S/D terminals, which nevertheless results in the same observation. Thus, the contact resistance difference of S/D terminals should be intrinsic.

Generally speaking, the contact resistance of a working TFT is affected by both the bulk resistance of the semiconductor underneath the contact metal and the interface properties of the contact itself. Because both RS and RD decrease at higher VGS just as RCH does, it means that the contact resistance is closely related to the bulk resistance of a-IGZO under the electrodes. This is easy to understand: as in staggered TFT structures, electrons in the channel accumulation layer have to travel across the bulk IGZO after being injected from the source electrode or before being collected by the drain electrode. However, since the gate-to-channel voltage decreases from source to drain, the bulk resistance at the source side should be smaller than that at the drain side. One would expect that RS should be smaller than RD if the bulk resistance is a dominant factor, which apparently contradicts the observation in this work. Therefore, other factors such as the interface properties of the a-IGZO and metal contacts should play an important role causing the S/D contact resistance asymmetry.

It has been reported that an Ti-oxide layer with a thickness of several nanometers can be formed at the IGZO–Ti interface due to the very high affinity of Ti with oxygen,[16,17] and consequently, an oxygen deficient region would be formed on top of the a-IGZO layer by redox reaction.[17,18] Accordingly, the band diagrams of the Ti–TiOx–IGZO junction in different conditions are illustrated in Fig. 4. Figure 4(a) depicts the schematic band diagram of separated Ti, TiOx, and a-IGZO layers. The electron affinity difference between a-IGZO (χIGZO = 4.16 eV[19]) and TiOx (χTiOx = 4.1 eV[20]) is only 0.06 eV. The Fermi level position (ECEF) of a-IGZO and TiOx can be determined by ECEF = kT ln (Nc/Nd), where the symbols have their common meaning. Here, Nc of TiOx and a-IGZO are 4.3× 1021 cm−3[21] and 5× 1018 cm−3,[19] respectively, while the donor concentration (Nd) of TiOx and the adjacent low-resistance a-IGZO is estimated as 1× 1018 cm−3[22] and 1× 1017 cm−3, respectively. Then the calculated Fermi level position of a-IGZO and TiOx are 0.102 eV and 0.218 eV below EC, respectively. Considering the small difference in electron affinity values and Fermi level positions of a-IGZO and TiOx, there should be no obvious energy barrier for electron transport across the a-IGZO and TiOx interface. On the other hand, the work function of Ti (ϕTi = 4.33 eV[23]) is considerably larger than the electron affinity of TiOx. Thus, as shown in Fig. 4(b), a Schottky barrier would be formed with a barrier height Φb = 0.23 eV when Ti is in direct contact with TiOx. Certainly, the actual value of Φb is also affected by interface charge density. The depletion region width (w) of a Schottky junction can be calculated by w = [2ɛs(Φbi+Va)/qNd]1/2, where Va is the applied bias voltage across the junction, ɛs and Φbi are the dielectric constant and build-in potential of the semiconductor, respectively. Considering the band diagram of the source contact (Fig. 4(c)), when positive VDS is applied, the TiOx–Ti Schottky junction is reversely biased. As a result, the depletion region would extend deep into the semiconductor layer, raising the resistance of the corresponding region. Assuming that the thickness of the TiOx layer is 5 nm and the voltage drop across the junction is 1 V, and taking ɛs,IGZO = 11.5ɛ0,[24] ɛs,TiOx = 70ɛ0,[22] the entire TiOx layer and the underlying a-IGZO layer would be fully depleted. For the case of the drain contact, as illustrated in Fig. 4(d), the originally small potential barrier (Φbi = 0.012 eV) for electron injecting from semiconductor to electrode can be nullified by the VDS applied, making the contact more ohmic. As a result, electrons can be easily collected by the drain electrode. Here it is also worth noting that the TiOx and a-IGZO layer are both n-type in nature. Thus, the applied voltage is unlikely to bend the conduction band of the semiconductor further upward to form an electron accumulation layer. The voltage drop across the junction should then be small and almost constant, which is in agreement with the potential profiles measured at high VGS in Fig. 3(a).

Fig. 4. Schematic energy band diagrams near the Ti and a-IGZO interface: (a) for separated system; (b) for contact without bias voltage; (c) for source contact where a reverse bias is applied, and (d) for drain contact where a forward bias is applied.
Fig. 5. Distribution of channel resistance per unit length r of the TFT with VDS = 5 V and VGS increasing from 7 V to 15 V. The shaded regions illustrate the topographic edges of the S/D electrodes.

The validity of the proposed Ti–TiOx–IGZO Schottky-like contact model can be further supported by the resistance distribution along the channel. The channel resistance per unit length at position x can be expressed as . As shown in Fig. 5, the resistance around the central channel region basically decreases from the drain side to the source side at different gate biases. However, a low resistance region near the drain electrode is clearly observed, which is a good indicator for the existence of a Ti-oxidation-induced oxygen-deficient region in a-IGZO, as it is known that the conductivity of a-IGZO is in positive correlation with the concentration of oxide vacancies. Meanwhile, at the source side, since the oxygen-deficient region of a-IGZO near the IGZO–TiOx interface is depleted, the low resistance region near the edge of the source electrode is absent.

4. Conclusion

In summary, based on an SKPM technique, the source and drain contact resistance of a working a-IGZO TFT with Ti-based S/D contact are separately extracted under different biasing conditions. The source and drain contact resistances are both found to decrease with gate voltage increasing, while the resistance of the source contact is always smaller than that of the drain contact. The asymmetry of S/D contact resistance is attributed to the difference in biasing conditions of the Schottky-like junction induced by the parasitic reaction of the Ti electrode and a-IGZO, which is confirmed by analyzing the channel resistance distribution. The overall contact resistance should be determined by both the bulk channel resistance under the contact electrodes and the properties of the metal-semiconductor junction at the contact interface. In future development, the interfacial oxidation mechanism of the metal electrode should be given more attention, or another metallization scheme should be used. The contact region of the active layer could be intentionally doped to reduce the depletion region width, which is helpful to reduce the overall contact resistance.

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