Cite this Article
Xin Yan-hui, Yuan Sheng, Liu Ming-tang, Liu Hong-xia, Yuan He-cai. Two-dimensional models of threshold voltage and subthreshold current for symmetrical double-material double-gate strained Si MOSFETs. Chinese Physics B, 2016, 25(3): 038502  
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Two-dimensional models of threshold voltage and subthreshold current for symmetrical double-material double-gate strained Si MOSFETs
Xin Yan-hui1, 2, Yuan Sheng1, Liu Ming-tang1, Liu Hong-xia2, †, , Yuan He-cai3
Department of Information and Engineering, North China University of WaterResources and Electric Power, Zhengzhou 450046, China
Key Laboratory for Wide Band Gap Semiconductor Materials and Devices of Education,School of Microelectronics, Xidian University, Xi’an 710071, China
Department of Mathematics and Information Science, North China University ofWater Resources and Electric Power, Zhengzhou 450046, China

 

† Corresponding author. E-mail: hxliu@mail.xidian.edu.cn

Project supported by the National Natural Science Foundation of China (Grant Nos. 61376099, 11235008, and 61205003).

Abstract
Abstract

The two-dimensional models for symmetrical double-material double-gate (DM-DG) strained Si (s-Si) metal–oxide semiconductor field effect transistors (MOSFETs) are presented. The surface potential and the surface electric field expressions have been obtained by solving Poisson’s equation. The models of threshold voltage and subthreshold current are obtained based on the surface potential expression. The surface potential and the surface electric field are compared with those of single-material double-gate (SM-DG) MOSFETs. The effects of different device parameters on the threshold voltage and the subthreshold current are demonstrated. The analytical models give deep insight into the device parameters design. The analytical results obtained from the proposed models show good matching with the simulation results using DESSIS.

PACS: 85.30.De;85.30.Hi;85.35.–p;
Keyword:double-material double-gate MOSFET;strained Si;threshold voltage;subthreshold current;
1. Introduction

As metal oxide semiconductor devices have been scaled down continuously, the channel length has been shortened, and how to suppress the short channel effects (SCEs), the drain induced barrier lowering (DIBL) effect and increasing the carrier transport efficiency becomes an attractive problem.[1–3] It becomes obligatory to find out the solution of this problem to improve the device performance. Many reports show that the mobility of the charge carriers can be enhanced through the strain technology.[4,5] A strain can result in an enhanced mobility, a modified lattice constant of the material, and an energy band structure to trap carriers. Thus, strained Si (s-Si) metal–oxide semiconductor field effect transistors (MOSFETs) have received a great deal of attention.[6] However, the higher degree of impact ionization leads to the higher density of interface traps which in turn degrades both DIBL and SCEs.[7]

Double-gate (DG) and multi-material gate MOSFET structures can suppress the SCEs and DIBL in an excellent way. Many theoretical and experimental studies have reported that the DG device has excellent short-channel effect immunity, an ideal subthreshold factor, and high transconductance.[8–10] Multi-material gate MOSFET structures, like double-material gate (DMG) MOSFETs, are proposed to suppress SCEs. These structures have two or three metals in the gate with different work functions.[11] Long et al. first proposed the DMG MOSFET structure,[12] and demonstrated that the novel structure can increase the carrier transportation efficiency and suppress SCEs. The DMG structure can improve the device performance.

In light of these facts, for the first time, we present the two-dimensional models of threshold voltage and subthreshold current for symmetrical DM-DG s-Si MOSFET by incorporating the double-material double-gate concept into the bi-axially strained channel device. By solving Poisson’s equation, the surface potential can be obtained. The proposed models are derived based on the surface potential. In the channel region, Poisson’s equation is solved by the parabolic approximation method with suitable boundary conditions.[13] The effects of various device parameters on the threshold voltage and the subthreshold current are demonstrated. Different length ratios are optimized to minimize the SCEs and the leakage current of the device. The derived analytical models give results that agree well with those of the 2D device simulator DESSIS.

2. Model formulation

The device structure is shown in Fig. 1. The gate is assumed to consist of two different metals, which have different work functions W1 and W2, known as the control gate and the screen gate whose corresponding lengths are L1 and L2. For nMOSFETs, the work function W2 of M2 is smaller. Here, W1 = 4.70 eV, W2 = 4.35 eV, ts−Si is the thickness of the s-Si film, tox is the thickness of the gate oxide, and gate length L = L1 + L2. The channel is divided into two different regions, region I and region II.

Fig. 1. Schematic diagram of symmetrical DM-DG s-Si MOSFET.
2.1. Surface potential model

The whole potential distribution is divided into the two regions in the s-Si layer. The potentials φ1 and φ2 belong to region I and region II, respectively. The x axis and the y axis are parallel and perpendicular to the channel, respectively. Poisson’s equation in the two regions can be written as[13]

where q is the electronic charge, ND is the doping concentration in the channel, and ɛSi is the dielectric constant of the s-Si film.

The potential of the s-Si layer in the vertical direction can be approximated as[13]

The coefficients Cj1(x) and Cj2(x), j = 1,2 are functions of x only. Due to the symmetry, we use the following boundary conditions to solve Poisson’s equation.

By applying Eq. (4) and

under the symmetry condition of the structure, the expression for the channel potential can be obtained. Substituting the channel potential into Eqs. (1) and (2), and setting y = 0, one obtains the equation of the surface potential in the two doping regions

with

Equation (9) is second-order non-homogenous differential, and the solutions can be written as

Using the boundary conditions of Eqs. (5)–(8), the coefficients A, B, C, and D can be solved as

where

The control gate region which has the higher work function mainly monitors the threshold voltage of the device. So the threshold voltage is determined by φS1 min.

By solving dφS1(x)/dx = 0 defined in Eq. (10), the position of the minimum surface potential can be calculated as

The minimum surface potential can be estimated as

The electric field pattern along the channel determines the electron transport velocity. The surface electric fields in region I and region II are given respectively by

2.2. Threshold voltage model

The conventional definition of threshold voltage of MOSFETs is the gate source voltage at which φSmin = 2φF,Si, where φF,Si is the difference between the extrinsic Fermi level in the bulk region and the intrinsic Fermi level.[14] By considering the effect of strain, the threshold condition of the front gate for the present symmetrical DM-DG s-Si MOSFET is modified as[14,15]

where

Substituting Eq. (20) into Eq. (17), we obtain the threshold voltage

where

2.3. Subthreshold current model

The diffusion phenomenon mainly determines the subthreshold current which is proportional to the carrier concentration at the position of the minimum channel potential. By applying the methodology used in Ref. [16], the subthreshold current can be expressed as

where , μn is the mobility of electron,[15,17] VT is the thermal voltage, and W is the width of the MOSFET. For the symmetric structure, the integral in Eq. (22) is divided into two parts along the channel thickness by the point ym = (1/2)ts−Si as[16]

It is considered that φ1min (y) varies linearly in both sections (0 ≤ y < ym and ym < y ≤ ts−Si). After some simplifications, the subthreshold current can be written as

where represents the constant electric field, represents the minimum potential at the interface between s-Si film and SiO2 layer, and φm = φ(x1min,ts−Si/2) is the minimum potential.

2.4. Results and discussion

In this paper, the analytical results obtained from the derived models are compared with the numerical simulation results using DESSIS. The doping concentration of the source–drain contact regions is NDS = 1 × 1020 cm−3. The device is simulated by using the drift-diffusion model for the carrier transport and the field-dependent mobility model because of the high electric fields in the device.

Figure 2 shows the surface potential along the channel length for different drain–source voltages. It can be observed that the minimum surface potential is located in the region under the control gate. A potential step exists near the interface of the two different gates for DM-DG MOSFET in comparison with single-material double-gate (SM-DG) MOSFET. It is the extra potential step that can increase the carrier transport. Because of the step potential, the additional drain voltage increase is absorbed under region II. In other words, region I is screened from the varied drain potential. Consequently, the drain voltage has little influence on region I. So the proposed novel structure can suppress the SCEs.

Fig. 2. Surface potentials in DM-DG and SM-DG MOSFETs with various drain voltages.

Figure 3 shows the surface electric fields in DM-DG s-Si MOSFET and SM-DG s-Si MOSFET. It can been observed that a peak electric field exists at the interface of region I and region II for the DM-DG s-Si MOSFET compared with the SM-DG s-Si MOSFET, which can increase the carrier mobility.

Fig. 3. Surface electric fields in DM-DG and SM-DG s-Si MOSFETs.

Figure 4 displays the threshold voltage for the proposed novel device with different strain Z. It is seen that the higher the Ge mole fraction Z, the lower the threshold voltage. The reason may be that the flatband voltage decreases, the built-in potential barrier in the source/drain-body decreases, and the inversion caused by the decrease in φth has an earlier onset. It can also be found that SCEs become apparent, and there is a sharp decrease when the channel length is below about 60 nm. This is due to the reason that the gate–source/drain charge sharing and source/drain–body depletion region becomes crucial for such short channel lengths.

Fig. 4. Threshold voltages with different strains.

Figure 5 shows the threshold voltage against the channel length at various control-to-screen gate length ratios (L1 : L2). It can be observed that the threshold voltage increases with increasing gate length ratio. It is demonstrated that the higher gate length ratio induces the higher channel barrier height. It also validates that the device has better suppression of SCEs with a higher gate length ratio.

Fig. 5. Threshold voltages with different gate length ratios.

Figure 6 investigates the subthreshold current characteristics for different strains, keeping the other parameters constant. The subthreshold current is higher for the higher strain. It may be attributed to that the built-in potential barrier between the channel and the source decreases.[7] Note that the model is developed for the subthreshold regime only, therefore there exists a large discrepancy between the present model and the simulation results for higher gate to source voltage.

Fig. 6. Variation of subthreshold current with strain.

Figure 7 analyses the effect of gate length ratio L1 : L2 on the subthreshold current characteristics. The higher gate length ratio helps to reduce the leakage current effectively. This may be attributed to the fact that the source/channel barrier height increases with an increase in the length of the control gate. Furthermore, the higher gate length ratio can increase the slope of the subthreshold current, indicating the switching characteristics are being improved.

Fig. 7. Variation of subthreshold current with gate length ratio.
3. Conclusion

The two-dimensional models of threshold voltage and subthreshold current for symmetrical double-material double-gate strained Si MOSFETs have been presented. The surface potential has been obtained for a different drain voltage. A detailed analysis of the impact of various device parameters on the threshold voltage and the subthreshold current has been given. It is demonstrated that the threshold voltage decreases and the subthreshold current increases with increasing strain. The leakage current and SCEs can be controlled desirably by increasing the gate length ratio. The analytical models give accurate results as compared to the simulations. The analytical models give valuable references to the physical parameter design.

Reference
1Trivedi V PFossum J G 2005 IEEE Electron Device Lett. 26 579
2Chaudhry AKumar M J 2004 IEEE Trans. Device Mater. Rel. 4 99
3Reddy G VKumar M J 2004 Microelectronics Journal 35 761
4Chaudhry ARoy J NJoshi G 2010 Journal of Semiconductors 31 104001
5Rim KAnderson RBoyd D 2003 Solid State Electronics 47 1133
6Ieong MDoris BKedzierski JRim KYang M 2004 Science 306 2057
7Kumar MDubye STiwari P KJit S 2013 J. Compt. Electron 12 20
8Rahman ALundstrom M S 2015 IEEE Trans. Electron Devices 62 2367
9Khakifirooz ANayfeh O MAntoniadis D 2009 IEEE Trans. Elec-tron Devices 56 1674
10Djeffal FMeguellati MBenhaya A 2009 Physica E 41 1872
11Kumar M JChaudhry A 2004 IEEE Trans. Electron Devices 51 569
12Long WOu HKuo J MChin K K1999IEEE Trans. Electron Devices46865
13Young K K 1989 IEEE Trans. Electron Devices 36 399
14Li JLiu H XLi BCao LYuan B 2010 Chin. Phys. B 19 107302
15Venkataraman VNawal SKumar M J2007IEEE Trans. Electron Devices54554
16Dey AChakravorty ADasgupta NDasgupta A 2008 IEEE Trans. Electron Device 55 3442
17Hamid H A EGuitart J RIniguez B 2007 IEEE Trans. Electron Devices 54 1402