Due to excellent physical and electrical properties, such as high breakdown electric field, wide bandgap, high thermal conductivity, and high electron saturation velocity, silicon carbide (SiC) has attracted increasing attention in high-temperature, high-power, and high-voltage devices.^[1–4] Metal–oxide–semiconductor field-effect transistors (MOSFETs) based on SiC have been regarded as a promising candidate for low-loss and fast power devices in advanced electronic systems.^[5] Significant progress in 4H–SiC MOSFETs has been demonstrated recently, with the fabrication of accumulation-mode MOSFETs (ACCUFETs),^[1] UMOSFET,^[2,6] DMOSFET,^[7–10] and RESURF MOSFET.^[11] SiC lateral MOSFETs are also very attractive as high-frequency power transistors, which can favorably compete with Si lateral MOSFET.^[11,12] SiC lateral devices have a distinctive advantage of being able to be integrated with other devices, reducing cost, and enhancing overall circuit performance.^[11,13]

The growth of high-quality gate oxides (SiO₂) with abrupt SiC/SiO₂ interfaces, containing a low density of interface traps D_it, is crucial for the fabrication of reliable MOSFETs with high channel mobility on 4H–SiC.^[14] The main source of the high D_it values has been attributed to residual carbon in the gate oxide layer,^[15] which was observed in the form of clusters^[16,17] distributed along the SiO₂/SiC interface. Although the chemical nature of these clusters is still not completely understood, it has been related to carbon complexes and silicon oxycarbides (SiC_xO_y)^[18] formed during the oxidation process. To form high-quality gate oxides with abrupt SiC/SiO₂ interfaces, here a sandwich gate oxidation method^[14] was used in our work. In this paper, our recent experimental work on N-channel enhancement lateral 4H–SiC MOSFFETs is reported. The lateral 4H–SiC MOSFFETs were successfully fabricated using ion implantation and sandwich (nitridation–oxidation–nitridation) type gate oxidation process. N-type MOS capacitors were also fabricated simultaneously with the lateral devices to investigate the interface properties of 4H–SiC/SiO₂. The properties of 4H–SiC/SiO₂ interfaces on N-type MOS capacitors were examined by the measurement of HF C–V, I–V, and G–V over a range of frequencies. High mobility of 38 cm²·V⁻¹·s⁻¹ was achieved for the fabricated lateral 4H–SiC MOSFFETs.

N-type 4°-off 4H–SiC (0001) Si-face epilayer with a net donor concentration of 6 × 10¹⁵ cm⁻³ was used to fabricate N-type MOS capacitors and lateral N-channel 4H–SiC MOSFFETs. A schematic cross section of the lateral N-channel 4H–SiC MOSFFETs and scanning electron microscopy (SEM) image of the fabricated device cross section are shown in Fig. 1. Figure 2 shows a top view photograph of a fabricated device with channel length of 10 μm and channel width of 200 μm. The P-well was formed by multiple-energy Al⁺ implantation of a box profile at three energies (40–350 keV). The N⁺ source and drain regions were created by nitrogen implantation of a box profile. The P⁺-region was also formed by high-dose Al⁺ implantation for obtaining good ohmic contacts on the p-well. After implantation, activation annealing was carried out in Ar at 1650 °C for 30 min. All wafers were protected with a carbon cap to minimize the surface roughness during annealing, and hereafter, the carbon cap was removed by low temperature thermal oxidation.

Fig. 1.

	Figure Option ViewDownloadNew Window
	Fig. 1. (a) Schematic cross section of the fabricated lateral N-channel 4H–SiC MOSFFETs and (b) scanning electron microscopy (SEM) image (cross section) of fabricated device.

Fig. 2.

	Figure Option ViewDownloadNew Window
	Fig. 2. Top-view of a fabricated lateral 4H–SiC MOSFET.

Prior to gate oxidation, the samples were prepared using RCA cleaning. The gate oxides were formed by the an NO/O₂/NO sandwich-type process, which consists of a 2% NO pre-anneal for 1 hour, followed by the bulk oxide growth in 5% dry O₂, finalized with a post oxidation anneal in 2% NO for an hour.^[2] Next, a polysilicon film was deposited and patterned to form the gate contact. Finally, source and drain Ohmic contacts were formed by evaporating Ti/Ni/Al (50 nm/100 nm/200 nm) and annealing with rapid thermal processing (RTP).

Thicknesses of the gate dielectric films were determined by both scanning electron microscopy (SEM), and capacitance–voltage (C–V) measurements. The channel length (L_ch) and width (W_ch) of the fabricated lateral MOSFETs were 10 μm and 200 μm, respectively. The MOS capacitors and MOSFET electrical properties (transfer and output characteristics) were measured with the Agilent B1505A semiconductor characterization system. All measurements presented in this paper were performed at room temperature.

Figure 3 shows the bidirectional capacitance–voltage (C–V) characteristics measured with various frequencies from 10 kHz to 1 MHz for the MOS capacitor fabricated with NO/O₂/NO sandwich oxidation. It can be seen that there is almost no hysteresis and frequency dispersion in the C–V curves. A relatively small hysteresis (about 0.025 V), corresponding to less border traps N_it near the interface (shown in Table 1), is observed in C–V curves. This is also confirmed by the conductance values, plotted in Fig. 4. For comparisons, the ideal C–V curve calculated using Poisson’s equation was also inserted in Fig. 3. It can be seen that the shape of the measured C–V curves is very similar to the theoretically calculated C–V curve (black dashed line), but there is a small voltage deviation between them, which indicates that there is relatively good quality of 4H–SiC/SiO₂ interface.

Fig. 3.

	Figure Option ViewDownloadNew Window
	Fig. 3. Bidirectional capacitance–voltage (C–V) characteristics measured with various frequencies from 10 kHz to 1 MHz for the MOS capacitor fabricated with NO/O2/NO sandwich oxidation.

Fig. 4.

	Figure Option ViewDownloadNew Window
	Fig. 4. Conductance–voltage (G–V) and capacitance–voltage (C–V) curves at 10 kHz for the MOS capacitor fabricated with NO/O2/NO sandwich oxidation.

Table 1.

Table 1.

Table 1. Parameters of the MOS capacitor extracted from the C–V curve measured at 10 kHz. . Parameters Value Nit/cm−2 1.93 × 108 ΔVFB/V −0.71 Neff/cm−2 1.39 × 1011 t/nm 58 Dit @0.2 eV/cm−2·eV−1 2 × 1011

Table 1. Parameters of the MOS capacitor extracted from the C–V curve measured at 10 kHz. .

Table 1 lists the dielectric thickness (t), flat-band voltage shift (ΔV_FB), effective dielectric charge (N_eff) extracted from C–V measurements. Parameter t was calculated from the maximum accumulation capacitance (C_ox). The N_eff was obtained from (−ΔV_FBC_ox)/qA, where ΔV_FB is the V_FB shift from the ideal value, A is the area of the capacitor, and q is the electronic charge. Figure 5 shows the distribution of interface state density (D_it) near the conduction band edge (E_c) of 4H–SiC estimated using the hi-lo C–V method. As shown in Fig. 5, the trap density (D_it) at 0.2 eV below the conduction band edge is as low as 2 × 10¹¹ cm⁻²·eV⁻¹, which indicates that NO/O₂/NO sandwich-type process can reduce the interface state density significantly.

Fig. 5.

	Figure Option ViewDownloadNew Window
	Fig. 5. Distribution of interface state density (Dit) near the conduction band edge (Ec) of 4H–SiC estimated using the hi-lo C–V method.

To evaluate the dielectric film breakdown characteristics, the typical current–electric field curves (I–E) of fabricated N-type 4H–SiC MOS structures is shown in Fig. 6, which is transformed from I–V curves. The electric field is approximated by (V_g–V_FB)/t, where V_g and t are the gate voltage and the oxide thickness. From Fig. 6, it shows that the critical breakdown electric field of SiO₂ is about 9.8 MV/cm at leakage current only 50 nA, and the statistical value of 20 measured MOS structures show that the median breakdown electric field is about 9 MV/cm.

Fig. 6.

	Figure Option ViewDownloadNew Window
	Fig. 6. Typical current versus electric field (I–E) of fabricated N-type 4H–SiC MOS structure.

Figure 7 shows the typical output characteristics of the fabricated lateral enhancement mode N-channel MOSFET with the gate voltage (V_g) from 0 V to 24 V and the drain–source voltage (V_DS) from 0 V to 15 V. The device exhibits a drain current of 900 μA at V_g = 24 V and V_DS = 15 V. The output characteristics exhibit excellent linear and saturation region. Figure 8(a) shows transfer characteristics at room temperature for the fabricated devices measured at a drain voltage of 100 mV. The threshold voltage of 9.5 V is obtained by linear extrapolation from the linear region of the transfer characteristics. Figure 8(b) shows the transconductance versus the gate voltage V_g, in which a peak value of 3.68 μS is reached at gate voltage of 14 V.

Fig. 7.

	Figure Option ViewDownloadNew Window
	Fig. 7. Typical output characteristics of the lateral enhancement mode N-channel MOSFET with gate voltage (Vg) from 0 V to 24 V and the drain–source voltage (VDS) from 0 V to 15 V.

Fig. 8.

	Figure Option ViewDownloadNew Window
	Fig. 8. (a) Transfer characteristics of the fabricated devices measured at a drain voltage of 100 mV and (b) the corresponding transconductance characteristics.

To examine the validity of the NO/O₂/NO sandwich-type gate oxidation method, gate voltage dependence of the field-effect mobility μ_FE was measured, and the V_g for the measurement ranges from 0 to 20 V. The μ_FE can be calculated from the following formula using transconductance characteristic at the drain voltage of 100 mV:

Fig. 9.

	Figure Option ViewDownloadNew Window
	Fig. 9. Field-effect mobility μFE as a function of gate voltage Vg in fabricated lateral MOSFETs.

The normally-off N-channel lateral 4H–SiC metal–oxide–semiconductor field-effect transistors (MOSFFETs) have been fabricated using sandwich (nitridation–oxidation–nitridation) type process in this paper. The interface state density near the conduction band edge of 4H–SiC was reduced to 2 × 10¹¹ eV⁻¹·cm⁻², breakdown field of the grown oxides was about 9.8 MV/cm, and peak field-effect mobility of 38 cm²·V⁻¹·s⁻¹ was achieved. It is found that the NO/O₂/NO sandwich-type oxidation process has a great potential as an alternative gate oxidation method in SiC MOS-based transistors.