A uniform doping ultra-thin SOI LDMOS with accumulation-mode extended gate and back-side etching technology
Zhang Yan-Hui1, Wei Jie1, Yin Chao1, Tan Qiao1, Liu Jian-Ping1, Li Peng-Cheng1, Luo Xiao-Rong1, 2, †,
       

3D temperature distributions at P = 1 mW/ μm for (a) AG-BE SOI LDMOS and (b) VLD SOI LDMOS.