A uniform doping ultra-thin SOI LDMOS with accumulation-mode extended gate and back-side etching technology

Zhang Yan-Hui¹, Wei Jie¹, Yin Chao¹, Tan Qiao¹, Liu Jian-Ping¹, Li Peng-Cheng¹, Luo Xiao-Rong^{1, 2, †,}

Equipotential contour distributions (20 V/contour) at breakdown (optimally) for (a) AG-BE SOI LDMOS (BV = 818 V), (b) AEG-VLD SOI LDMOS (BV = 800 V), (c) VLD SOI LDMOS (BV = 776 V), and (d) conventional SOI LDMOS (BV = 144 V); (e) lateral surface electric field component.