† Corresponding author. E-mail:

Project supported by the National Natural Science Foundation of China (Grant No. 61376080), the Natural Science Foundation of Guangdong Province, China (Grant No. 2014A030313736), and the Fundamental Research Funds for the Central Universities, China (Grant No. ZYGX2013J030).

An analytical model for a novel triple reduced surface field (RESURF) silicon-on-insulator (SOI) lateral double-diffused metal–oxide–semiconductor (LDMOS) field effect transistor with n-type top (N-top) layer, which can obtain a low on-state resistance, is proposed in this paper. The analytical model for surface potential and electric field distributions of the novel triple RESURF SOI LDMOS is presented by solving the two-dimensional (2D) Poisson’s equation, which can also be applied to single, double and conventional triple RESURF SOI structures. The breakdown voltage (BV) is formulized to quantify the breakdown characteristic. Besides, the optimal integrated charge of N-top layer (*Q*_{ntop}) is derived, which can give guidance for doping the N-top layer. All the analytical results are well verified by numerical simulation results, showing the validity of the presented model. Hence, the proposed model can be a good tool for the device designers to provide accurate first-order design schemes and physical insights into the high voltage triple RESURF SOI device with N-top layer.

Owing to its ideal dielectric isolation, higher speed, less parasitic effect, and higher integration, silicon-on-insulator (SOI) technology is of great benefit to high voltage lateral double-diffusion metal–oxide–semiconductor (LDMOS) devices and has been widely developed for a variety of power ICs, such as automotive driver IC, display driver IC, high-voltage switching IC, LED driver IC, etc.^{[1–7]} One of the main issues when designing LDMOS is the trade-off between breakdown voltage (BV) and specific on-resistance (*R*_{on,sp}).^{[8–14]} Triple reduced surface field (RESURF) technology^{[15–21]} is an excellent method in mass manufacture to achieve the tradeoff between BV and *R*_{on,sp}. With a floating p-type buried (P-buried) layer inserted into n-type drift region, the triple RESURF structure provides dual conduction paths to reducing *R*_{on,sp}. Because of the three-sided vertical depletion, the drift region doping concentration can be three times higher than that in single RESURF, with the BV maintained. Compared with the conventional triple RESURF SOI LDMOS, the novel triple RESURF SOI LDMOS with n-type top (N-top) layer can achieve a lower *R*_{on,sp}, with a high BV maintained, because the incorporation of N-top layer has a weak effect on the breakdown characteristics and provides a lower on-resistance surface conduction path. Hence, the novel triple RESURF SOI LDMOS with N-top layer can achieve a more optimal distribution of impurities for triple RESURF structure to improve the tradeoff between the BV and *R*_{on,sp}. Some similar work of the triple RESURF LDMOS with N-top layer on bulk-silicon is reported in our previous work.^{[20,21]}

In the present paper, an analytical model for the novel triple RESURF SOI LDMOS with low on-state resistance is presented. The model for the surface potential and electrical field distributions, which is based on the two-dimensional (2D) Poisson’s equation, is obtained. The analytical expressions of surface potential and electric field can be simply applied to single, double and conventional triple RESURF SOI LDMOS. Further, the analytical results of BV and optimal integrated charge of N-top layer (*Q*_{ntop}) for the novel triple RESURF SOI LDMOS are obtained. The analytical results of the presented model can show great agreement with the numerical simulation results. Hence, the proposed model can give guidance for designer to optimize the novel triple RESURF SOI LDMOS with N-top layer.

Figure *N*_{PB}. Compared with the structure of the conventional triple RESURF SOI LDMOS, a high-doped N-top layer with doping concentration *N*_{T} is introduced at the surface of N-well. As a result, lower *R*_{on,sp} is achieved because of extra majority carriers, which provides a lower on-resistance surface conduction path. The doping concentration of the N-well is *N*_{nwell}. The N-well is divided into five regions along the edges of P-buried layer and N-top layer, and their boundary positions are given by: *x* = 0, *L*_{1}, *L*_{2}, *L*_{d}, and *y* = 0, *t*_{1}, *t*_{2}, *t*_{d}. The *t*_{ox} is defined as the thickness of the SOI layer.

The cross section of triple RESURF SOI LDMOS with N-top layer.

When the device is biased in the off-state and the N-well is fully depleted, the potential function in the silicon must satisfy 2D Poisson’s equation, yielding:

*q*is the electric charge,

*ɛ*

_{s}is the dielectric constant for silicon,

*N*

_{1}=

*N*

_{3}=

*N*

_{5}=

*N*

_{nwell},

*N*

_{2}=

*N*

_{T}+

*N*

_{nwell}, and

*N*

_{4}=

*N*

_{PB}−

*N*

_{nwell}. The boundary conditions for the potential function are given by

*K*=

*ɛ*

_{s}/

*ɛ*

_{ox}and

*ɛ*

_{ox}is the dielectric constant for SiO

_{2}. Equation (

Substituting Eqs. (

*N*

_{1,eff}=

*N*

_{3,eff}=

*N*

_{nwell}, and

*N*

_{2,eff}=

*N*

_{nwell}−

*η*

_{1}

*N*

_{PB}+

*η*

_{2}

*N*

_{T}. The

*t*,

*η*

_{1}, and

*η*

_{2}denote the characteristic thickness value of drift region, the vertical doping factors of P-buried layer, and N-top layer, respectively, and are given as follows:

*i*= 1, 2, 3 and

*L*

_{i − 1}≤

*x*≤

*L*

_{i},

*V*

_{i, eff}=

*qN*

_{i, eff}

^{t2}/

*ɛ*

_{s},

*V*

_{0}= 0,

*V*

_{3}=

*V*

_{d},

*L*

_{0}= 0,

*L*

_{3}=

*L*

_{d}, and

*y*= 0. The

*L*

_{1}and

*L*

_{2}are the positions of two boundaries between N-well and N-top layer. The

*V*

_{1}and

*V*

_{2}are the surface potentials of two boundaries between drift region and N-top layer and can be obtained from the condition (Eqs. (

*N*

_{PB}= 0,

*N*

_{T}= 0), double (

*t*

_{1}= 0) and conventional triple RESURF (

*N*

_{T}= 0) SOI LDMOS.

Solving the potential function partial respect to *y* and substituting it into Eqs. (

*O*

_{2}in the N-top/N-well junction is larger than that at

*O*

_{3}in the N-well/N

^{+}-drain junction because the P-buried layer is introduced and lengths of N-top layer and P-buried layer are close to the length of drift region. Therefore, there are two surface electric field peaks at

*O*

_{1}and

*O*

_{2}. The lengths of P-buried layer and N-top layer are both almost equal to the length of drift region. So assuming

*L*

_{1}= 0 and

*L*

_{2}=

*L*

_{d}, the vertical breakdown can only occur at either

*O*

_{4}or

*O*

_{5}. The electric field at

*O*

_{4}for the N-top/P-buried junction is larger than that at

*O*

_{2}due to the influence of vertical electric field at

*O*

_{4}. Hence, the lateral breakdown voltage

*BV*

_{lat}can be obtained from

*E*(0,0) =

*E*

_{c}when the breakdown occurs at

*O*

_{1}. The

*BV*

_{lat}can be described as:

*BV*

_{ver1}can be obtained from

*E*

_{2y}(

*L*

_{1},

*t*

_{1}) =

*E*

_{c}when the breakdown occurs at

*O*

_{4}, and

*BV*

_{ver2}can be obtained from

*E*

_{5y}(

*L*

_{2},

*t*

_{d}) =

*E*

_{c}when the breakdown occurs at

*O*

_{5}. The

*BV*

_{ver1},

*BV*

_{ver2}, and

*BV*are given as follows:

The analytical *Q*_{ntop} can be obtained when the N-well is fully depleted and the breakdown occurs at *O*_{4}. The *Q*_{ntop} includes the charges of N-well and N-top layer. The vertical depletion extension *d*_{1} into the N-top layer can be given as follows:

*Q*

_{ntop}for the N-top layer is expressed as

In this paper, all the numerical results are obtained by 2D device simulator MEDICI and the analytical results are obtained by the analytical model. Figures ^{+} -drain junction. Figures *N*_{PB} = 0, *N*_{T} = 0) and double (*t*_{1} = 0) RESURF SOI LDMOS without being modified. The single and double RESURF SOI LDMOS obtain BV values of 445 V and 447 V, respectively. The analytical results of surface potential and electric field distributions for single and double RESURF SOI LDMOS show good agreement with the numerical simulation results.

Numerical and analytical profiles of surface potential and electric field of (a) novel triple RESURF SOI LDMOS, (b) conventional triple RESURF SOI LDMOS, (c) single RESURF SOI LDMOS, and (d) double RESURF SOI LDMOS in drift region.

Figure *R*_{on,sp}, and power figure of merit (FOM, defined as BV^{2}/*R*_{on,sp}) versus *N*_{nwell} for the conventional triple RESURF SOI LDMOS with *L*_{d} = 35 μm, *L*_{1} = 2 μm, *L*_{2} = 31 μm, *t*_{1} = 1 μm, *t*_{2} = 2 μm, and *t*_{d} = 8 μm. The conventional triple RESURF SOI LDMOS has a correspondingly optimized *N*_{PB} for any given *N*_{nwell}. *R*_{on,sp} decreases with the increase of *N*_{nwell}. With the increase of *N*_{nwell} from 3.2× 10^{15} cm^{−3} to 4.4× 10^{15} cm^{−3}, BV is maintained at a similar value of above 450 V firstly. With the continuous increase of *N*_{nwell} from 4.4× 10^{15} cm^{−3} to 5.6× 10^{15} cm^{−3}, BV decreases. With *N*_{nwell} = 4.4 × 10^{15} cm^{−3}, the conventional triple RESURF SOI LDMOS obtains a BV of 454 V and a *R*_{on,sp} of 40 mΩ·cm^{2}, yielding a highest FOM of 5.15 MW/cm^{2}. Figure *R*_{on,sp} versus *N*_{T} for the novel and conventional triple RESURF SOI LDMOS, and analytical maximum *N*_{T} with *L*_{d} = 35 μm, *L*_{1} = 2 μm, *L*_{2} = 31 μm, *t*_{1} = 1 μm, *t*_{2} = 2 μm, *t*_{d} = 8 μm, and *N*_{nwell} = 4.4× 10^{15} cm^{−3}. When *N*_{T} = 0× 10^{16} cm^{−3}, the device is a conventional triple RESURF SOI LDMOS which achieves a BV of 454 V and a *R*_{on,sp} of 40 mΩ·cm^{2}. As *N*_{T} increases, the N-top layer is formed. BV can maintain the same value, and *R*_{on,sp} decreases because an additional N-top layer introduces more majority carriers to significantly reduce *R*_{on,sp}, which alleviates the inherent tradeoff between *R*_{on,sp} and BV. Then, BV decreases when *N*_{T} continues to increase. For any given *N*_{T}, the device has a correspondingly optimized *N*_{PB} when the drift region is fully depleted. When *N*_{T} is 1.6 × 10^{16} cm^{−3}, the novel triple RESURF SOI LDMOS can achieve a low *R*_{on,sp} of 31.3 mΩ·cm^{2} which is 22% lower than that of conventional triple RESURF SOI LDMOS at the same BV level. According to Eq. (*t*_{1} = 1 μm, the analytical maximum *N*_{T} is 1.56 × 10^{16} cm^{−3}. When *N*_{T} exceeds the value, BV decreases with the increase of *N*_{T}.

(a) Numerical results of BV, *R*_{on,sp}, and FOM versus *N*_{nwell} for conventional triple RESURF SOI LDMOS, (b) numerical results of BV and *R*_{on,sp} versus *N*_{T} for novel and conventional triple RESURF SOI LDMOS, and analytical maximum *N*_{T}.

Figure *L*_{d} = 35 μm, *L*_{1} = 2 μm, *L*_{2} = 31 μm, *t*_{1} = 1 μm, *t*_{2} = 2 μm, *t*_{d} = 8 μm, and *N*_{nwell} = 4.4× 10^{15} cm^{−3}. With an extra N-top layer, the novel triple RESURF SOI LDMOS has more majority carriers at the surface of N-well than the conventional triple RESURF SOI LDMOS. Meanwhile, in order to keep charge balance for a high BV, the increased *N*_{PB} is needed. The two structures have similar doping profiles of N-well below P-buried layer due to the same *N*_{nwell}. Figure *R*_{on,sp}. Therefore, compared with the conventional triple RESURF SOI LDMOS, the novel triple RESURF SOI LDMOS with N-top layer can achieve a lower *R*_{on,sp} while maintaining a high BV.

Figure *R*_{on,sp} versus *N*_{PB} at different values of *N*_{T} for the novel triple RESURF SOI LDMOS when *L*_{d} = 35 μm, *L*_{1} = 2 μm, *L*_{2} = 31 μm, *t*_{1} = 1 μm, *t*_{2} = 2 μm, *t*_{d} = 8 μm, and *N*_{nwell} = 4.4 × 10^{15} cm^{−3}. For the numerical results, with increase in *N*_{PB}, BV has a maximum value when the N-well is fully depleted for any given *N*_{T}. The *R*_{on,sp} is almost constant with the increase of *N*_{PB} due to the nearly equivalent n-type impurity in the n-type drift region. As *N*_{T} increases, *R*_{on,sp} is reduced for the same BV first. Then, BV decreases when *N*_{T} continues to increase. The analytical BV values obtained from Eqs. (

Numerical and analytical results of BV and numerical results of *R*_{on,sp} versus *N*_{PB} at different *N*_{T} values for the novel triple RESURF SOI LDMOS.

Figure *Q*_{ntop} at different values of *t*_{1} for the novel triple RESURF SOI LDMOS and the analytical maximum *Q*_{ntop} when *L*_{d} = 35 μm, *L*_{1} = 2 μm, *L*_{2} = 31 μm, *t*_{d} = 8 μm, and *N*_{nwell} = 4.4× 10^{15} cm^{−3}. The thickness of P-buried layer in the simulations is 1 μm. With the increase of *Q*_{ntop}, the BV can be first maintained at a similar value and then decreases because of too high a dose of N-top layer. According to Eq. (*Q*_{ntop} is *ɛ*_{s}*E*_{c}/*q*. The analytical maximum *Q*_{ntop} is an upper theoretical bound for the dose of surface conduction path, which can guide the designer in achieving an optimal distribution of impurities in the drift region to optimize the tradeoff between the BV and *R*_{on,sp}. The critical electric field *E*_{c} is a weak function of the doping. With the decrease of *t*_{1}, the concentration of the N-top layer will increase at the same *Q*_{ntop}, which causes the increase of *E*_{c}. So, the analytical maximum *Q*_{ntop} will increase with the decrease of *t*_{1}. The analytical maximum *Q*_{ntop} values are obtained at different *t*_{1} values and are also shown in Fig. *t*_{1} = 1.0 μm, the analytical maximum *Q*_{ntop} is around 2.0 × 10^{12} cm^{−2}. Hence, compared with the conventional triple RESURF SOI LDMOS, the novel triple RESURF SOI LDMOS can maintain a high BV and a lower *R*_{on,sp} with *Q*_{ntop} ≤ 2.0 × 10^{12} cm^{−2} at *t*_{1} = 1.0 μm.

Numerical results of BV versus *Q*_{ntop} at different *t*_{1} values for novel triple RESURF SOI LDMOS and the analytical maximum *Q*_{ntop}.

In this work, an analytical model for the surface potential and electric field distributions of the novel triple RESURF SOI LDMOS with N-top layer are presented. The corresponding analytical model for the surface potential and electric field distributions are also applicable to single, double and conventional triple RESURF SOI structures. Besides, the analytical BV and maximum *Q*_{ntop} are obtained. The analytical maximum *Q*_{ntop} is an upper theoretical bound which is useful to control the implantation doses and energy for the N-top layer. All the analytical results obtained from the given expressions can show fair agreement with the numerical results, indicating the validity of the presented model. Consequently, the proposed analytical model can be a good tool for the designer to optimize the novel triple RESURF SOI LDMOS with N-top layer. The novel triple RESURF SOI LDMOS can achieve a more optimized distribution of impurities in the drift region to further improve the tradeoff between BV and *R*_{on,sp} than the conventional triple RESURF SOI LDMOS.

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