The generation current in the metal-oxide-semiconductor field-effect transistor (MOSFET) is a leakage current that results from the interface traps which serve as the generation sites when the channel is in the non-equilibrium state.^{[1, 2]} Since this type of current is closely related to the traps, it is widely used to detect the damage created by the hot carrier and the negative bias temperature instability (NBTI) stresses.^{[3– 5]} Scoot et al. applied this current to study the radiation damage in x-ray imagers and proposed a new pixel design based on gated diode structures that will provide the improved image quality.^[6] Our previous paper studied the degradation of MOSFET by the method of generation current transconductance, ^[7] then we discussed the effect of substrate bias on the generation current and recently set up a theoretical model for this current.^{[8, 9]} In addition, the generation current was also involved in several researches about the fin field-effect transistor and its reliability issues.^{[10, 11]}

All the generation currents used in the above studies are gate-modulated. This type of current can be measured by the method of sweeping the gate which makes the channel state change from accumulation, depletion to inversion. In the measurement, the drain bias V_D is fixed to keep the quasi-Fermi level of the substrate minority carrier unchanged, and therefore it plays the role of maintaining the non-equilibrium state in the depletion region during the formation of gate-modulated generation current. However, V_D is often varied in the work condition of MOSFET meaning that the non-equilibrium state is dynamic. Since the dynamic non-equilibrium state should affect the generation function of interface traps, a new important problem arises: what is the feature of the generation current under the dynamic non-equilibrium condition? It can also be expressed as: how does the drain modulate the generation current? Nonetheless, little attention has been paid to this problem so far.

On the basis of the above discussion, this paper aims to reveal the features of drain-modulated generation current I_DMG and expound the deep physical mechanisms behind these features. The nMOSFET with a 4-nm gate oxide thickness was used in this paper. Through analyzing the changes of I_DMG versus V_D, their relationship and the related physical mechanisms are discussed deeply by combining experimental results with theoretical analysis.

The device used in this paper was an nMOSFET with an n⁺ poly-Si gate fabricated by using 90-nm complementary-metal-oxide-semiconductor (CMOS) technology. The gate oxide thickness t_ox was 4  nm with width/length = 6  μ m/0.35  μ m. The threshold voltage of the device was 0.49  V. For the drain-modulated generation current measurement, floating the source and grounding the substrate, the drain was swept from − 0.2  V to 1.0  V. The gate bias V_G was fixed at 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, and 0.8  V. The drain current was I_DMG. The schematic diagram of the I_DMG measurement is shown in Fig.  1. All electrical tests were performed by using a Keithley 4200 precision semiconductor parameter analyzer. In addition, all the simulations were done using the MATLAB software.

Fig.  1.

	Figure Option ViewDownloadNew Window
	Fig.  1. The schematic diagram of the drain modulated generation current IDMG measurement with nMOSFET.

The I_DMG is an interface trap-induced drain leakage current because of the Shockley– Read– Hall (SRH) effect. In the SRH model, the electron density n_s and hole density p_s at the interface Si/SiO₂ can change the generation rate g. The relationship between them is^[12]

where n_s and p_s can be written as

with n₀ and p₀ the substrate minority and majority carrier density, respectively, p₀ = N_A and β = kT/q, m is the adjustment coefficient for the practical device and m = 1 in the ideal situation, while φ _s is the surface potential given by

When the substrate doping is not heavy, the first and fourth items in Eq.  (3) are too small and can be ignored. Thus φ _s is dominated by (V_G– V_FB). If V_G > 0  V, φ _s > 0  V because V_FB is negative generally. The change of V_D results in the change of n_s at the given V_G according to Eq.  (2), which eventually causes g changes. Since V_D is larger than 0, n_s decreases with the increase in V_D.

When n_s ≥ p₀, the channel Si surface is stepped into the inversion state, then a larger number of electrons make the interface traps lose their generation roles and g is zero. In this case, V_D can be deduced according to the expression of n_s in Eq.  (2) as follows:

As V_D increases, n_s decreases which leads to the Si surface presenting the depletion state, then g should increase with the increase in V_D.

When n_s ≤ n_i/5 that is one-tenth of 2n_i, the change of n_s has no effect on g. In this case, V_D should be

For p_s, it cannot affect g only if p_s < = n_i/5. According to Eq.  (2), there is

so combining Eqs.  (3) and (6), it is deduced as

which shows that V_G should be very small or even negative in the case of p_s = n_i/5 under V_FB < 0  V when p₀ is not heavy. Hence, if V_G is larger than this critical value, p_s has no influence on g in theory. In a word, g should almost keep constant when the value of V_D satisfies Eq.  (5).

Figure  2(a) shows a schematic diagram of the relationship between V_D and g. As V_D increases with a given V_G, g increases and the channel state changes from inversion to depletion. Moreover, the depletion divides into two depletion states: I state and II state. Figure  2(b) shows the simulated g versus V_D curves under different given V_G. It can be seen that the simulated g curve complies with the schematic diagram basically and the g curve shifts rightwards as V_G increases with the reason that V_G induces the change of φ _s.

Fig.  2.

	Figure Option ViewDownloadNew Window
	Fig.  2. (a) A schematic diagram of the relationship between VD and g. (b) Curves of the simulated g versus VD. In the simulation, tox = 4  nm and p0 = NA = 4 × 1015  cm− 3, m = 1.25 and VFB = − 0.35  V.

Since I_DMG is in direct proportion to g, that is

where r = aqN_itσ v_th, a is the gate area, q is the single electron charge, N_it is the density of interface traps, σ is the cross section of a trap, and v_th is the thermal velocity, the variation of the I_DMG curve has the same trend as the g curve. Once V_G is given, I_DMG increases with V_D increasing at first and afterwards steps into saturation in which I_DMG cannot increase any more.

Figure  3 shows the experimental I_DMG curves. For a given V_G, the I_DMG curve is almost zero at the beginning of V_D increasing from − 0.2  V, then all of a sudden it augments. After exceeding its maximum, the curves start to drop with V_D increasing and finally present a peak shape. It can be seen that the curves shift rightwards and the peaks almost keep constant as V_G changes from 0.1 to 0.8 V. Figure  3 also shows the simulated I_DMG curves based on g in the Fig.  2(b). Compared with the simulated curve, the experimental curve is basically consistent with it from the inversion to depletion I state.

Fig.  3.

	Figure Option ViewDownloadNew Window
	Fig.  3. Comparison of the experimental IDMG (symbol line) and simulated IDMG (dash line) based on Fig.  2(b). Here, w/l = 6  μ m/0.35  μ m. Nit = 2 × 1011  cm− 2, and σ = 4 × 10− 13  cm− 2. Other structure parameters are the same as those in Fig.  2(b).

In order to better confirm the validity of the theory in depletion I state, we analyze the peak point which is the boundary point of depletion I state. Because I_DMG is proportional to g, g is the maximum at the I_DMG peak. At this peak, n_s = n_i/5. It defines V_GP and V_DP as the V_G and V_D corresponding to the I_DMG peak respectively. According to Eqs.  (2) and (6), V_GP and V_DP have the following relationship:

Since the third and fourth items in Eq.  (9) are too small and can be ignored when N_A < 10¹⁶  cm^{− 3}, equation (9) can be simplified as

Figure  4 shows the relationship between V_GP and V_DP extracted from the experimental curves in Fig.  3. It can be seen that V_GP has a linear relationship with V_DP. The fitted equation is: V_GP = sV_DP, where s = 1.24, which agrees with Eq.  (10) and s is very close to the value of m (m = 1.25) in the simulated curves in Fig.  3. Hence, the agreement fully proves the validity of the theory about the depletion state mentioned above. However, the experimental curve in Fig.  3 after reaching the peak cannot step into saturation like the simulated curve, but drops quickly with V_D increasing. This experimental result implies that the physical mechanism behind Fig.  2 does not hold in the depletion II state. Further, it can be deduced that the transport of interface generation current suffers some kind of inhibition after reaching the maximum value.

Fig.  4.

	Figure Option ViewDownloadNew Window
	Fig.  4. Relationship between VGP and VDP extracted from the experimental IDMG curves in Fig.  3.

To seek the real physical mechanism hidden in the I_DMG falling edge, figure  5(a) presents the conductance C_D of experimental I_DMG from Fig.  3. C_D can indicate the ability of V_D controlling I_DMG. It can be seen that there are two C_D peaks located in the rising edge and falling edge of I_DMG, C_DRP and C_DFP, respectively. All the C_DRP and C_DFP keep constant in Fig.  5(a). Obviously, V_G seems to have little influence on the C_D curve and just shifts the C_D curve rightwards. Namely, V_G cannot affect the ability of V_D controlling I_DMG curves. Thus the problem of V_D controlling the I_DMG curve can be transformed into that of the drain-gate voltage V_DG (V_DG = V_D− V_G) controlling the I_DMG curve. The benefit of this transformation is to compress the group of I_DMG curves and to well make the implicit information present. Then, figure  5(b) presents the I_DMG curves under V_DG. V_DG at the I_DMG peak is defined as V_DGP and then V_DGP = V_DP − V_GP = (1/s − 1) V_GP = − 0.2V_GP. Since V_GP is not beyond 0.8  V, the range of V_DGP is very small. Therefore, the current peaks are located at about V_DG ≈ 0  V. In Fig.  5(b), the left side of the curve corresponds to the rising edge of the I_DMG versus V_D curve, and the right side corresponds to the falling edge of the I_DMG versus V_D curve. Because the difference between the simulation and experimental results in Fig.  3 is mainly focused on the falling edge of the V_D versus I_DMG curve, it needs to focus on the right side of the I_DMG versus V_DG curve. Further, ignoring the slight shift of the current peak, a common feature in all the curves is that the curves drop under V_DG > 0  V as V_DG increases. To sum up, V_DG controls the change of the falling edge of the experimental I_DMG curve in Fig.  3.

Fig.  5.

	Figure Option ViewDownloadNew Window
	Fig.  5. (a) Conductance of the curves from Fig.  3, and (b) variations of the experimental IDMG with VDG extracted from Fig.  3.

Since V_DG is the drain-to-gate voltage drop, it affects the Si surface of the channel around the drain. Hence, the whole channel is divided into two regions: main channel region A and region B that is around the drain, as shown in Fig.  6. The generation rates of these two regions are g₁ and g₂, respectively. At a given V_G, the channel steps into depletion II state in Fig.  1 and the increase of V_D almost cannot change g₁. However, V_DG should increase with V_D increasing. As a consequence, the bending of the Si energy band at region B decreases and lessens the surface potential φ _s. When p_s > n_i/5 in region B, g₂ starts to decrease, as can be seen in Fig.  6(a). As V_D continues to increase, the channel depletion region returns to region A completely and an accumulation state can be formed in region B, as shown in Fig.  6(b). So the generation function of the interface traps in region B is shielded and g₂ is close to zero. The channel electrons created by the trap’ s generation are eventually collected by the drain. Based on the above discussion, the electron transport of the whole channel electron is subject to g₂. Namely, g₂ dominates the magnitude of the generation current. On the basis of the above discussion, g₂ should lessen with V_D increasing that is beyond V_DP. Thus, the generation current decreases. As V_D further increases, region B steps into the accumulation state, g₂ becomes zero, and the generation current disappears. As can be seen from Fig.  3, the experimental curves in the depletion II state just conform to this logical deduction.

Fig.  6.

	Figure Option ViewDownloadNew Window
	Fig.  6. Schematic diagrams of channel states as VD varies. (a) Depletion situation of B region, and (b) accumulation situation of B region.

If the above theory of V_DG controlling the falling edge of I_DMG is reasonable, the generation current versus the V_DG curve should obey it no matter which measurement method is used. Figure  7(a) shows the curve of gate-modulated generation current I_GMG versus V_DG, which is obtained by scanning V_Gwith fixing V_D. It can be seen that the I_GMG curve changes from rising to falling when V_DG > 0  V. This phenomenon agrees with the case of I_DMG, which considerably indicates that the theory suits I_GMG. More, the curve of recombination current versus V_DG should present the same shape as the I_DMG curve because the recombination current also results from the SRH effect. Figure  7(b) shows the curve of the gate-modulated recombination current I_GMR versus V_DG under V_D < 0  V. It can also be seen that the I_GMR curve firstly goes up and then drops when V_DG > 0  V. In general, the rationality of the theory is verified considerably by these two additional experiments above.

Fig.  7.

	Figure Option ViewDownloadNew Window
	Fig.  7. (a) Variations of gate-modulated generation current (IGMG) with VDG, and (b) variations of gate-modulated recombination current (IGMR) with VDG.

On the basis of the theory’ s rationality, the variation of I_DMG in depletion II state is discussed in detail as follows. The gate-to-drain voltage drop V_GD dominates φ _s, the V_G in Eq.  (3) should be substituted by V_GD. Due to V_GD = − V_DG, the surface potential around the drain corner φ _SD is

Thus, p_s is deduced as

which increases quickly after exceeding n_i/5 and then p_s ≫ n_i and n_s ≪ n_i. Since p_s plays the dominant role in the falling stage of I_DMG, g₂ is simplified as

As mentioned before, the first and fourth terms of Eq.  (11) can be ignored, then substituting Eq.  (11) into Eq.  (13), g₂ can be written as

In order to meet the practical devices, an additional accommodation-coefficient n is introduced in Eq.  (14), then g₂ becomes

which indicates that g₂ decreases with V_DG increasing when V_G is given. According to Eq.  (8), I_DMG also shows the exponential decay relationship with V_DG. Defining I₀ = rb, the theoretical model of I_DMG in the falling edge can be written as

In order to verify the correctness of Eq.  (17), figure  8(a) extracts the experimental I_DMG curves at different fixed V_G from Fig.  5(b) and fits them. The expression obtained by the curve fitting is given by

with c and t the fitting coefficients. The experimental model of Eq.  (18) mainly has the same form as the theoretical model of Eq.  (17), in which I_DMG has the exponential attenuation relation with V_DG. To further test the matching degree of the theory and experiment, figure  8(b) extracts the fitting coefficient t because t decides the degree of the exponential attenuation. As can be seen, t basically does not vary with the variation of V_G, which is about 0.08  V or 80  mV. Since the thermal potential β = kT/q = 26  mV, t ≈ 3β . If n = 3 in Eq.  (17), the decay degree with V_DG of Eq.  (18) becomes the same as that of Eq.  (17). Hence, the value of t verifies the reasonability of the theoretical model of Eq.  (17). Further, this result fully shows the accuracy of the mechanism of V_DG controlling the falling edge of I_DMG proposed in the above sections.

Fig.  8.

	Figure Option ViewDownloadNew Window
	Fig.  8. (a) The falling edges of experimental and fitted IDMG versus VDG curves, and (b) variations of t with VD extracted from panel (a).

The characteristics of the drain-modulated generation current I_DMG induced by interface traps in nMOSFETs are discussed. The change of V_D induces the changes of φ _s and thus changes n_s and p_s, which results in the formation of I_DMG. During this formation, the channel suffers from the inversion state, depletion I state to depletion II state as V_D increases with the given V_G. The results of experiment and simulation agree well with each other in the inversion and depletion I states. However, the simulated curve keeps constant and the experimental curve drops quickly when the channel steps into the depletion II state. It is found that the falling edge of the experimental I_DMG curve is close with the drain-to-gate voltage V_DG. Since V_DG affects the Si surface of the channel around the drain corner, the whole channel is divided into two regions: the main channel, region A, and region B, which is around the drain corner. The generation rate of region B is g₂ dominating the generation current. V_DG increases with V_D increasing, which lessens φ _s. Therefore, g₂ increases and results in the drop of the I_DMG curve. As V_D further increases, region B is into the accumulation state and then the generation function of the interface trap is screened by a large number of holes. Consequently, I_DMG disappears. The experiments of the gate-modulate generation and recombination currents are also applied to verify the reasonability of the above mechanism that is V_DG controlling the falling edge of the I_DMG curve. Based on this mechanism, a theoretical model is set up in which I_DMG has the exponential attenuation relation with V_DG. Finally, the fitting coefficient of the experimental curves t is extracted. It is found that t = 80  mV. These results fully show the accuracy of the above mechanism.