†Corresponding author. E-mail: firstname.lastname@example.org
‡Corresponding author. E-mail: email@example.com
*Project supported by the Young Scientists Fund of the National Natural Science Foundation, China (Grant No. 61401373), the Fundamental Research Funds for Central University, China (Grant No. XDJK2013B004 and 2362014XK13), and the Research Fund for the Doctoral Program of Southwest University, China (Grant No. SWU111030).
A combination of self-aligned fluoride-based plasma treatment and post-gate rapid thermal annealing was developed to fabricate a novel 120-nm T-shaped gate normally-off metamorphic Al0.49In0.51As/Ga0.47In0.53As HEMT device on a Si substrate grown by metal-organic chemical vapor deposition (MOCVD). A shift of the threshold voltage, from −0.42 V to 0.11 V was obtained and the shift can be effectively adjusted by the process parameter of CF4 plasma treatment. Furthermore, a side benefit of reducing the leakage current of the device up to two orders of magnitude was also observed. E-mode transistors with 120 nm gate length own fT up to 160 GHz and fmax of 140 GHz. These characteristics imply the potential of the fluoride-based plasma treatment technology for the fabrication of monolithic enhancement/depletion-mode mHEMTs, which also encourage the massive production with this low-cost technology.
Over the past decades, III– V materials are paid intensive and continuous attention as channel alternatives for n-FET in the future complementary metal oxide semiconductor (CMOS) technology. GaInAs, as a channel material, closely matches with InP, and have shown tremendous potential due to their high electron mobility and low power operations.[1, 2] Recently, AlInAs/GaInAs high electron mobility transistors (HEMTs) on a Si substrate, which effectively take advantage of the high carrier drift velocity of GaInAs channel HEMT, the large wafer size, and the mechanical strength of Si substrate, are expected to be the most promising devices for high-speed and low-power digital logic applications in the future.[3, 4] Moreover, AlInAs/GaInAs enhancement-mode (E-mode) HEMT can be integrated with the corresponding depletion-mode (D-mode) HEMT to form direct-coupled FET logic (DCFL) circuits in a simple circuit configuration, which can be combined with the mainstream Si-based CMOS process technology to implement ultra-high-speed and very-large-scale logic digital integrated circuits on Si substrate in the foreseeable future. However, conventional GaInAs channel HEMT is a D-mode device, and the realization of high-performance E-mode devices will pave the way for fabrication of high-speed GaInAs channel E/D-mode CMOS-like DCFL circuits for digital applications. Therefore, most of the recent studies used different technologies, such as the gate-recess etching,  the buried-gate technology, [7, 8] and fluorine-based plasma treatment[9– 11] to develop E/D-mode AlInAs/GaInAs HEMTs on the same epi-wafer. However, the conventional gate recess process suffers the poor uniformity of threshold voltage (Vth) and controllability of etching depth, which is very important for the fabrication of digital circuits. Similarly, a gate-recess step is also required by the buried-gate technology, and the large leakage current is a challenging issue. Currently, many studies mainly reported the fluorine plasma treatment technology in AlGaN/GaN HEMTs on Si substrate, and few study in AlInAs/GaInAs HEMTs.
In this paper, in order to reduce the leakage current and improve the comprehensive DC and RF characteristics, a combination of self-aligned fluoride-based plasma treatment and post-gate rapid thermal annealing, which is a similar process to realize ultra-shallow junctions in advanced Si technology, was developed to realize an 120-nm E-mode AlInAs/GaInAs mHEMT on Si substrate. The effects of plasma immersion ion implantation (PIII) during the fluoride-based treatment were analyzed in detail. Finally, a significant reduction of the leakage current up to two orders of magnitude was successfully achieved. The Vth can be effectively shifted from − 0.42 V to 0.11 V by adjusting the process parameter of CF4 plasma treatment, and fT of 160 GHz was obtained.
The schematic of epitaxial structure and TEM cross-section micrograph, including composite buffers, of the Al0.49In0.51As/Ga0.47In0.53As metamorphic HEMT (mHEMT) is shown in Fig. 1. All layers were grown on 4-inch (001)-oriented semi-insulating Si substrates in an Aixtron AIX-200/4 MOCVD reactor. The Hall measurement of the grown material indicates that the two-dimensional electron gas (2-DEG) sheet carrier density is greater than 4.0 × 1012 cm2 and the mobility is over 8000 cm2/V· s at room temperature.
From bottom to top, the Al0.49In0.51As/Ga0.47In0.53As mHEMT consists of a 10-nm GaAs nucleation layer, 450-nm HT-GaAs layer, 880-nm composite LT/HT InP-lattice-matched buffer layer grown at 500 ° C/600 ° C, 30-nm Ga0.47In0.53As strain balance layer, 300-nm HT/LT-Al0.49In0.51As buffer layer, 30-nm Ga0.47In0.53As channel, 5-nm undoped Al0.49In0.51As spacer layer, Si-delta-doping, 13-nm undoped Al0.49 In0.51As Schottky layer, and 13-nm Ga0.47 In0.53As cap layer heavily doped with Si (7 × 1018 cm− 3). A 30-nm thin Ga0.47In0.53As lightly compressively-strained layer was introduced to balance the residual strain between HT/LT-InP buffer layer and HT/LT-Al0.49In0.51As buffer layer in the composite buffer structure. The high-resolution x-ray diffraction (HRXRD) measurement was performed to obtain the full width at half maximum (FWHM) of the GaAs buffer of 328 arcsec and InP buffer of 320.3 arcsec. The good crystalline quality characterized by these FWHM values is important for the manufacture of good-performance devices. Moreover, the TEM cross-sectional image of the whole composite buffer layers shown in Fig. 1 clearly shows few misfit dislocations and smooth surface. 60-degree threading dislocations, obtained by the formula related with FWHM of the HRXRD measurement, were confined in the buffer and is comparable to our previous work.
The combination of self-aligned fluoride-based plasma treatment and post-gate rapid thermal annealing was developed to fabricate an 120-nm E/D-mode AlInAs/GaInAs mHEMTs on Si substrate. Firstly, E/D-mode mHEMTs were isolated by wet chemical etching, followed by source/drain definition and ohmic metallization by evaporating Ni/Ge/Au/Ge/Ni/Au using an electron beam evaporator. Then a two-stage electron beam lithography technology was used to fabricate the 120-nm T-shape gate. SiNx (100 nm) was deposited, followed by coating ZEP520 electron beam (EB) resist and the first EB exposure and development. Then SiNx film is etched by CHF3/CF4/O2 reactive ion etching (RIE) to define the gate footprint and mechanically supports the T-shaped gate. The second EB lithography was employed to form gate head pattern by bilayer polymethylmethacrylate/polymethylglutarimide (PMMA/PMGI) EB resist technology, which is similar to our previous work. After the gate-recess etching with succinic-based acid to completely remove the highly doped Ga0.47In0.53As cap layer and expose the Al0.49In0.51As barrier layer, devices were treated by CF4 plasma in an RIE system, followed by gate metallization and lift-off for the E-mode mHEMTs. The followed CF4 plasma treatment can be directly processed in the Al0.49In0.51As barrier layer and the F− ions introduced by CF4 plasma treatment can be effectively enhanced. Then the sample was annealed in nitrogen at 400 ° C for 10 min to recover the plasma-induced damages in Al0.49In0.51As barrier and channel. This plasma treatment can effectively convert the treated devices from the D-mode to E-mode mHEMTs with proper CF4 treatment parameters, and the magnitude of threshold voltage shift depends on the treatment conditions, such as plasma power and treatment time. The post-gate rapid thermal annealing has been found to have no effect on the threshold voltage shift introduced by the plasma treatment. Finally, the electrodes of E/D-mode mHEMTs devices were followed by the e-beam evaporation of Ti/Au and lift off.
To characterize the surface morphology of gate-recess region, figure 2 shows atomic force microscope (AFM) images of device with and without CF4 plasma treatment across a scanned area of 10 × 10 μ m2. The corresponding root mean square (RMS) values are 2.16 nm and 2.76 nm, respectively. It can be found that devices suffer low surface damage during the CF4 plasma treatment.
To examine the distribution profile of negatively charged F− ions introduced by CF4 plasma treatment and ascertain how far the F− ion tail extends, E/D mode HEMTs were probed by the secondary ion mass spectrum (SIMS) with and without the CF4 plasma treatment. Figure 3 shows the SIMS measurement as a function of depth from the surface for sample a without CF4 treatment and sample b treated by 150 W CF4 treatment for 150 s, respectively. It can be found from Fig. 3 that the concentration of F atoms is the highest near the surface and drops by one order of magnitude in the channel. It can be deduced that the fluorine ions produced by the CF4 plasma were mainly incorporated into the device surface and the fluorine ions can be neglected at the GaInAs channel layer.
The corresponding conduction-band profiles with and without the fluoride ions incorporated in AlInAs barrier layer is shown in Fig. 4, where the electric field formed from the immobile negatively charged F− ions bends the conduction band in AlInAs barrier and causes an additional barrier height Φ F. Conduction band in the GaInAs channel layer is over the Fermi level, which makes the 2-DEG completely depleted and converts HEMT from D-mode to E-mode. Moreover, the raised barrier height Φ F effectively enhances the gate Schottky barrier height, resulting in the significant suppression to the reverse and forward current of gate Schottky diode of AlInAs/GaInAs HEMT.
Typical current– voltage (I– V) and transfer characteristics of Al0.49In0.51As/Ga0.47In0.53As mHEMTs on Si substrate with and without CF4 plasma treatment are measured by HP4156A semiconductor parameter analyzer, as shown in Fig. 5. The maximum drain current (IDSmax) was 560 mA/mm for D-mode mHEMT and 220 mA/mm for E-mode mHEMT treated by CF4 plasma at power of 150 W for 150 s at VGS = 0.6 V and VDS = 1.5 V. The reduction of IDSmax for E-mode mHEMT is largely attributed to the reduction of the channel electrons partly depleted from immobile F− ions at the same biased voltage. The Vth is extracted by the linear extrapolation of drain current at gate bias corresponding to the peak transconductance (gm) in IDS– VGS transfer characteristics, and the Vth of D-mode mHEMT is − 0.42 V, while it is 0.11 V for E-mode mHEMT. Similarly, these immobile negative charges is incorporated into the AlInAs barrier during the CF4 plasma treatment and the channel electron is effectively depleted, resulting in the shift of Vth. The peak gm was 760 mS/mm for the D-mode mHEMT and 330 mS/mm for the E-mode mHEMT at VDS = 1.0 V. It should be noted that the fluoride ions might get implanted to reach the channel so that the saturation current of the E-mode HEMT dropped to about 50% of the original value in the untreated D-mode HEMT. Therefore, CF4 treatment and the barrier thickness should be further optimized to improve the saturation drain current and the peak gm of the E-mode HEMT.
The dependence of Vth on the power of CF4 plasma treatment is shown in Figs. 6(a) and 6(b), where the shift of Vth increases as the plasma power increases. The shift characteristics of Vth is attributed to the fact that the increased plasma power makes the ionization rate of CF4 enhanced, resulting in the increase of F− ions, and makes the diffusion depth of F− ions be closer to the GaInAs channel, resulting in the effective depletion of 2-DEG in the channel. Moreover, the linear relation between the shift of Vth and plasma power indicates that the precise control on Vth can be achieved in the fabrication process. However, as shown in Fig. 6(b), the native doping ions induced by MOCVD sometimes restrict the shift in Vth, resulting in some “ quasi-zero” Vth in process, which is harmful to integration of E/D-mode HEMT to form DCFL circuits with CF4 treatment technique. Thus, the combination of CF4 treatment with the “ gate sinking” method, which in fact demonstrates great potency, should be further studied.
The gate current of AlInAs/GaInAs mHEMTs after CF4 plasma treatments at different RF powers is shown in Fig. 6(c). The reverse-biased gate leakage currents were dramatically reduced after CF4 plasma treatment at power of 150 W for 120 s. The gate leakage current is reduced by two orders of magnitude at VGS = − 3 V due to the fact that the raised gate Schottky barrier height Φ F introduced by implanted F− ions suppresses the gate current.
The RF performance of the devices was assessed using on-wafer small signal S-parameter measurements on 0.12 × 100 μ m2 mHEMTs on Si substrate by cascade microtech probes and an HP8722 network analyzer from 0.1 to 39.1 GHz. On-wafer open and short de-embedding structures were used to determine the parasitic capacitance of the probe pads and to de-embed the short-circuit current gain |H21|. The current-gain cutoff frequency (fT) and the maximum available gain (fmax) were calculated by extrapolating at − 6 dB per octave. As shown in Fig. 7, fT/fmax was about 190/140 GHz for D-mode mHEMT and 160/140 GHz for the E-mode mHEMT treated by the combination of post-gate rapid thermal annealing process and the CF4 plasma treatment with an power of 150 W for 120 s. Obviously, the RF characteristics suffer low degradation, and post-gate annealing effectively recovers the 2-DEG mobility degraded by the plasma treatment. So the self-aligned CF4 plasma treatment incorporated with proper post-gate annealing process is necessary for fabricating high-performance RF E-mode AlInAs/GaInAs mHEMT on Si substrate.
A self-aligned CF4 plasma treatment technique was successfully developed to fabricate AlInAs/GaInAs mHEMTs on Si substrate by MOCVD, and the dramatically reduced leakage current and the significant threshold voltage shift from D-mode to E-mode were obtained due to the negatively charged fluorine ions incorporated in the AlInAs barrier layer during the CF4 plasma treatment. The post-gate rapid thermal annealing process was combined to recover 2-DEG mobility degraded by the plasma treatment, and E-mode device suffers low surface-damage and a good RF performance was effectively obtained. The nearly linear relation between the shift in Vth and plasma power implies the possibilities of the fabrication of monolithic E/D-mode mHEMTs and ultra-high-speed and large-scale DCFL logic digital integrated circuits on Si substrate with the low-cost technology developed.