Influence of ultra-thin TiN thickness (1.4 nm and 2.4 nm) on positive bias temperature instability (PBTI) of high-<bold><em> k</em></bold>/metal gate nMOSFETs with gate-last process<xref ref-type="fn" rid="cpb151524fn1">*</xref>

Influence of ultra-thin TiN thickness (1.4 nm and 2.4 nm) on positive bias temperature instability (PBTI) of high- k/metal gate nMOSFETs with gate-last process*

Qi Lu-Wei†, Yang Hong, Ren Shang-Qing, Xu Ye-Feng, Luo Wei-Chun, Xu Hao, Wang Yan-Rong, Tang Bo, Wang Wen-Wu‡, Yan Jiang, Zhu Hui-Long, Zhao Chao, Chen Da-Peng, Ye Tian-Chun

Vg waveform. After stress, discharging occurs at V _discharge,1 for 1000 s. The gate bias is then changed to V _discharge,2 for the next discharging phase and the same procedure is applied.