Please wait a minute...
Chin. Phys. B, 2020, Vol. 29(10): 108501    DOI: 10.1088/1674-1056/ab9f28
INTERDISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY Prev   Next  

New embedded DDSCR structure with high holding voltage and high robustness for 12-V applications

Jie-Yu Li(李婕妤)1,2, Yang Wang(汪洋)1,2,†, Dan-Dan Jia(夹丹丹)1,2, Wei-Peng Wei(魏伟鹏)1,2, and Peng Dong(董鹏)3
1 School of Physics and Optoelectronics, Xiangtan University, Xiangtan 411105, China
2 Hunan Engineering Laboratory for Microelectronics, Optoelectronics and System on A Chip, Xiangtan 411105, China
3 SuperESD Microelectronics Technology CO., LTD., Changsha 410100, China
Abstract  

A new dual directional silicon-controlled rectifier based electrostatic discharge (ESD) protection device suitable for 12-V applications is proposed in this paper. The proposed device (NPEMDDSCR) is based on the embedded DDSCR (EMDDSCR) structure, in which the P+ electrode and P+ injection are removed from the inner finger. Compared with the conventional modified DDSCR (MDDSCR), its high holding voltage meets the requirements for applications. Compared with the embedded DDSCR (EMDDSCR), it has good conduction uniformity. The MDDSCR, EMDDSCR, and NPEMDDSCR are fabricated with an identical width in a 0.5-μm CDMOS process. In order to verify and predict the characteristics of the proposed ESD protection device, a transmission line pulse (TLP) testing system and a two-dimensional device simulation platform are used in this work. The measurements demonstrate that the NPEMDDSCR provides improved reliability and higher area efficiency for 12 V or similar applications. The measurement results also show that the NPEMDDSCR provides higher robustness and better latch-up immunity capability.

Keywords:  DDSCR      holding voltage      failure current      conduction uniformity  
Received:  09 May 2020      Revised:  12 June 2020      Accepted manuscript online:  23 June 2020
PACS:  85.30.De (Semiconductor-device characterization, design, and modeling)  
  85.30.Rs (Thyristors)  
  73.40.Lq (Other semiconductor-to-semiconductor contacts, p-n junctions, and heterojunctions)  
Corresponding Authors:  Corresponding author. E-mail: wangyang@xtu.edu.cn   
About author: 
†Corresponding author. E-mail: wangyang@xtu.edu.cn
* Project supported by the National Natural Science Foundation of China (Grant Nos. 61704145, 61774129, and 61827812), the Natural Science Foundation of Hunan Province, China (Grant No. 2019JJ50609), and the Key Technology Program of Changsha City, China (Grant No. kq1902042).

Cite this article: 

Jie-Yu Li(李婕妤), Yang Wang(汪洋)†, Dan-Dan Jia(夹丹丹), Wei-Peng Wei(魏伟鹏), and Peng Dong(董鹏) New embedded DDSCR structure with high holding voltage and high robustness for 12-V applications 2020 Chin. Phys. B 29 108501

Fig. 1.  

Cross-section view of 2-finger DDSCR of (a) MDDSCR, (b) EMDDSCR, and (c) NPEMDDSCR.

Fig. 2.  

Equivalent circuit of 2-finger DDSCR of (a) MDDSCR, (b) EMDDSCR, and (c) NPEMDDSCR.

Fig. 3.  

TCAD simulated cross section of (a) MDDSCR, (b) EMDDSCR, and (c) NPEMDDSCR.

Fig. 4.  

Total current-flow-line at (a) the trigger point, (b) the holding point, and (c) the high ESD current pulse. In the legends of the figure, Si3N4 and SiO2 symbolize Si3N4 and SiO2 respectively. Number 3.43e + 04 equals to 3.43 × 104.

Fig. 5.  

Impact ionization of (a) MDDSCR, (b) EMDDSCR, and (c) NPEMDDSCR.

Fig. 6.  

Comparisons of TLP characteristic among MDDSCR, EMDDSCR, and NPEMDDSCR.

Device name Forward/reverse VBD/V Vt1/V Vh/V It2/A HBM/kV
MDDSCR forward 17 19.60 10.40 11.80 17.7
reverse 17 19.50 7.63 13.07 19.6
EMDDSCR forward 17 19.74 10.60 6.81 10.2
reverse 17 19.61 10.88 6.55 9.8
NPEMDDSCR forward 17 18.50 14.60 11.70 17.6
reverse 17 19.60 15.19 10.96 16.4
Table 1.  

TLP data for MDDSCR, EMDDSCR, and NPEMDDSCR.

[1]
Zeng J, Dong S, Liu J J, Han Y, Zhong L, Wang W H 2015 IEEE Trans. Electron Dev. 62 606 DOI: 10.1109/TED.2014.2381511
[2]
Chen R, Han J W, Zheng H S, Yu Y T, Shangguan S P, Feng G Q, Ma Y Q 2015 Chin. Phys. B 24 046103 DOI: 10.1088/1674-1056/24/4/046103
[3]
Wang Y, Jin X L 2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits July, 2019 Hangzhou, China DOI: 10.1109/IPFA47161.2019.8984875
[4]
Liu Z W, Liu J J, Dong S S, Han Y 2010 IEEE Electron Dev. Lett. 31 845 DOI: 10.1109/LED.2010.2050575
[5]
Zhang S, Dong S R, Wu X J, Zeng J, Zhong L, Wu J 2015 Chin. Phys. B 24 108502 DOI: 10.1088/1674-1056/24/10/108502
[6]
Dai C T, Ker M D 2018 IEEE Trans. Electron Dev. 65 798 DOI: 10.1109/TED.2017.2785121
[7]
Liu Z W, He J, Liu J J, Liu J Z, Miao M, Dong S R 2012 IEEE Solid-State and Integrated Circuit Technology October, 2012 Xi’an, China DOI: 10.1109/ICSICT.2012.6467917
[8]
Huang X Z, Liu J J, Liu Z W, Liu F, Liu J Z, Cheng H 2016 IEEE Electron Dev. Lett. 37 1311 DOI: 10.1109/LED.2016.2598063
[9]
Huang X Z, Liu Z W, Liu F, Liu J Z, Song W Q 2017 Electron. Lett. 53 1274 DOI: 10.1049/el.2017.2390
[10]
Wang Y, Lin N, Cui X. L, Jin X L 2016 Electric. Eng. Technol. 11 1921 DOI: 10.5370/JEET.2016.11.5.1362
[11]
Guan J, Wang Y, Hao S W, Zheng Y F, Jin X L 2017 IEEE Electron Dev. Lett. 38 1716 DOI: 10.1109/LED.2017.2766686
[12]
Huo M X, Ding K B, Han Y, Dong S R, Du X Y, Huang D H, Song B 2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits July, 2009 Suzhou, China DOI: 10.1109/IPFA.2009.5232711
[13]
Wang Y, Jia D D, Chen X J, Jin X L 2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits July, 2019 Hangzhou, China DOI: 10.1109/IPFA47161.2019.8984915
[1] New DDSCR structure with high holding voltage for robust ESD applications
Zi-Jie Zhou(周子杰), Xiang-Liang Jin(金湘亮), Yang Wang(汪洋), and Peng Dong(董鹏). Chin. Phys. B, 2021, 30(3): 038501.
[2] Enhanced gated-diode-triggered silicon-controlled rectifier for robust electrostatic discharge (ESD) protection applications
Wenqiang Song(宋文强), Fei Hou(侯飞), Feibo Du(杜飞波), Zhiwei Liu(刘志伟), Juin J. Liou(刘俊杰). Chin. Phys. B, 2020, 29(9): 098502.
[3] Design of a novel high holding voltage LVTSCR with embedded clamping diode
Ling Zhu(朱玲), Hai-Lian Liang(梁海莲), Xiao-Feng Gu(顾晓峰), Jie Xu(许杰). Chin. Phys. B, 2020, 29(6): 068503.
[4] Improving robustness of GGNMOS with P-base layer for electrostatic discharge protection in 0.5-μm BCD process
Fei Hou(侯飞), Ruibo Chen(陈瑞博), Feibo Du(杜飞波), Jizhi Liu(刘继芝), Zhiwei Liu(刘志伟), Juin J Liou(刘俊杰). Chin. Phys. B, 2019, 28(8): 088501.
[5] High holding voltage SCR for robust electrostatic discharge protection
Zhao Qi(齐钊), Ming Qiao(乔明), Yitao He(何逸涛), Bo Zhang(张波). Chin. Phys. B, 2017, 26(7): 077304.
[6] Novel substrate trigger SCR-LDMOS stacking structure for high-voltage ESD protection application
Ma Jin-Rong (马金荣), Qiao Ming (乔明), Zhang Bo (张波). Chin. Phys. B, 2015, 24(4): 047303.
[7] An improved GGNMOS triggered SCR for high holding voltage ESD protection applications
Zhang Shuai (张帅), Dong Shu-Rong (董树荣), Wu Xiao-Jing (吴晓京), Zeng Jie (曾杰), Zhong Lei (钟雷), Wu Jian (吴健). Chin. Phys. B, 2015, 24(10): 108502.
No Suggested Reading articles found!