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Chin. Phys. B, 2019, Vol. 28(10): 106802    DOI: 10.1088/1674-1056/ab3e62
Special Issue: SPECIAL TOPIC — A celebration of the 100th birthday of Kun Huang
SPECIAL TOPIC—A celebration of the 100th birthday of Kun Huang Prev   Next  

Charge trapping memory device based on the Ga2O3 films as trapping and blocking layer

Bing Bai(白冰)1, Hong Wang(王宏)1, Yan Li(李岩)1, Yunxia Hao(郝云霞)1, Bo Zhang(张博)1, Boping Wang(王博平)1, Zihang Wang(王子航)1, Hongqi Yang(杨红旗)1, Qihang Gao(高启航)1, Chao Lü(吕超)2, Qingshun Zhang(张庆顺)1, Xiaobing Yan(闫小兵)1,3
1 Key Laboratory of Optoelectronic Information Materials of Hebei Province, Key Laboratory of Digital Medical Engineering of Hebei Province, College of Electron and Information Engineering, Hebei University, Baoding 071002, China;
2 Department of Electrical and Computer Engineering, Southern Illinois University Carbondale, Carbondale, Illinois 62901, United States;
3 Department of Materials Science and Engineering, National University of Singapore, Singapore 117576, Singapore
Abstract  We present a new charge trapping memory (CTM) device with the Au/Ga2O3/SiO2/Si structure, which is fabricated by using the magnetron sputtering, high-temperature annealing, and vacuum evaporation techniques. Transmission electron microscopy diagrams show that the thickness of the SiO2 tunneling layer can be controlled by the annealing temperature. When the devices are annealed at 760 ℃, the measured C-V hysteresis curves exhibit a maximum 6 V memory window under a ±13 V sweeping voltage. In addition, a slight degradation of the device voltage and capacitance indicates the robust retention properties of flat-band voltage and high/low state capacitance. These distinctive advantages are attributed to oxygen vacancies and inter-diffusion layers, which play a critical role in the charge trapping process.
Keywords:  charge trapping memory      SiO2 tunneling layer      annealing temperature  
Received:  07 June 2019      Revised:  22 August 2019      Accepted manuscript online: 
PACS:  68.35.Fx (Diffusion; interface formation)  
  85.25.Hv (Superconducting logic elements and memory devices; microelectronic circuits)  
  06.60.Ei (Sample preparation)  
  21.10.Ft (Charge distribution)  
Fund: Project supported by the National Natural Science Foundation of China (Grant Nos. 61674050 and 61874158), the Top-notch Youth Project in Hebei Province, China (Grant No. BJ2014008), the Outstanding Youth Project of Hebei Province, China (Grant No. F2016201220), the Outstanding Youth Cultivation Project of Hebei University, China (Grant No. 2015JQY01), the Project of Science and Technology Activities for Overseas Researcher, China (Grant No. CL201602), the Institute of Baoding Nanyang Research-New Material Technology Platform, China (Grant No. 17H03), the Project of Distinguished Young of Hebei Province, China (Grant No. A2018201231), the Training Program of Innovation and Entrepreneurship for Undergraduates, China (Grant Nos. 201710075013 and 2017075), the Support Program for the Top Young Talents of Hebei Province, China (Grant No. 70280011807), Training and Introduction of High-level Innovative Talents of Hebei University, China (Grant No. 801260201300), Hundred Persons Plan of Hebei Province, China (Grant Nos. 606999919001, 606999919013, 606999919014, and 801260201300), and Innovation Funding Project of Hebei Province, China (Grant No. CXZZBS2019030).
Corresponding Authors:  Qingshun Zhang, Xiaobing Yan     E-mail:  87086486@qq.com;yanxiaobing@ime.ac.cn,xiaobing_yan@126.com

Cite this article: 

Bing Bai(白冰), Hong Wang(王宏), Yan Li(李岩), Yunxia Hao(郝云霞), Bo Zhang(张博), Boping Wang(王博平), Zihang Wang(王子航), Hongqi Yang(杨红旗), Qihang Gao(高启航), Chao Lü(吕超), Qingshun Zhang(张庆顺), Xiaobing Yan(闫小兵) Charge trapping memory device based on the Ga2O3 films as trapping and blocking layer 2019 Chin. Phys. B 28 106802

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