Non-depletion floating layer in SOI LDMOS for enhancing breakdown voltage and eliminating back-gate bias effect

doi:10.1088/1674-1056/22/4/047701

Abstract A non-depletion floating layer silicon-on-insulator (NFL SOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) is proposed and the NFL-assisted modulated field (NFLAMF) principle is investigated in this paper. Based on this principle, the floating layer can pin the potential for modulating bulk field. In particular, the accumulated high concentration of holes at the bottom of the NFL can efficiently shield the electric field of the SOI layer and enhance the dielectric field in the buried oxide layer (BOX). At variation of back-gate bias, the shielding charges of NFL can also eliminate back-gate effects. The simulated results indicate that the breakdown voltage (BV) is increased from 315 V to 558 V compared to the conventional reduced surface field (RESURF) SOI (CSOI) LDMOS, yielding a 77% improvement. Furthermore, due to the field shielding effect of the NFL, the device can maintain the same breakdown voltage of 558 V with a thinner BOX to resolve the thermal problem in an SOI device.

Keywords: breakdown voltage back-gate bias effect self-heating effect silicon-on-insulator

Received: 02 May 2012
Revised: 11 September 2012
Accepted manuscript online:

PACS:	77.55.df	(For silicon electronics)
	85.30.De	(Semiconductor-device characterization, design, and modeling)
	51.50.+v	(Electrical properties)

Corresponding Authors: Zheng Zhi
E-mail: zhizh734@gmail.com

Cite this article:

Zheng Zhi (郑直), Li Wei (李威), Li Ping (李平) Non-depletion floating layer in SOI LDMOS for enhancing breakdown voltage and eliminating back-gate bias effect 2013 Chin. Phys. B 22 047701

[1]	Narayanan E M S and Amaratunga G 1995 Proc. ISPSD p. 218
[2]	Luo X R, Yao G L, Chen X, Wang Q, Ge R and Udreab F 2011 Chin. Phys. B 20 028501
[3]	Wang Y G, Luo X R, Ge R, Wu L J, Chen X, Yao G L, Lei T F, Wang Q, Fan J and Hu X R 2011 Chin. Phys. B 20 077304
[4]	Zhang J, He J, Zhou X Y, Zhang L N, Ma Y T, Chen Q, Zhang X K, Yang Z, Wang R F, Han Y and Chan M 2012 Chin. Phys. B 21 047303
[5]	Hu S D, Zhang L, Luo X R, Zhang B, Li Z J and Wu L J 2011 Chin. Phys. Lett. 28 128503
[6]	Wu L J, Hu S D, Zhang B, Luo X R and Li Z J 2011 Chin. Phys. B 20 087101
[7]	Wang Z G, Zhang B, Fu Q, Xie G and Li Z J 2012 IEEE Electron. Dev. Lett. 33 703
[8]	Luo X R, Zhang B, Lei T F, Li Z J, Xiao Z Q, Hsu W C W and Udrea F 2010 IEEE Trans. Electron. Dev. 57 3033
[9]	Wang W L, Zhang B, Li Z J and Chen W J 2009 IEEE Electron. Dev. Lett. 30 68
[10]	Park I Y and Salama C A T 2006 IEEE Trans. Electron. Dev. 53 1909
[11]	Qiao M, Zhang B, Li Z J and Fang J 2007 Electron. Lett. 43 1231
[12]	Duan B X, Yang Y and Zhang B 2010 Solid-State Electron. 54 685
[13]	Schwantes S, Florian T, Stephan T, Graf M and Dudek V 2005 IEEE Trans. Electron. Dev. 52 1649
[14]	Luo J X, Chen J, Zhou J H, Wu Q Q, Chai Z, Yu T and Wang X 2012 Chin. Phys. B 21 056602
[15]	Nakagawa A, Yamaguchi Y, Yasuhara N, Hirayama K and Funaki H 1996 IEDM Tech. Dig. p. 477
[16]	Udrea F, Popescu A and Milne W 1997 Proc. IEEE Int. SOI Conf. p. 102
[17]	Hu S D, Zhang B, Li Z J and Luo X R 2010 Chin. Phys. B 19 037303
[18]	TMA MEDICI 4.2., Palo Alto, CA: Technology Modeling Associates Inc.
[19]	Ludikhuize A W 2000 Proc. ISPSD p. 11
[20]	O'Shea S J, Atta R M, Murrell M P and Welland M E 1995 J. Vac. Sci. Technol. B 13 1945

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Non-depletion floating layer in SOI LDMOS for enhancing breakdown voltage and eliminating back-gate bias effect

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