Drain-induced barrier lowering effect for short channel dual material gate 4H silicon carbide metal–semiconductor field-effect transistor

doi:10.1088/1674-1056/21/9/097302

Abstract Sub-threshold characteristics of the dual material gate 4H-SiC MESFET (DMGFET) are investigated and the analytical models to describe the drain-induced barrier lowering (DIBL) effect are derived by solving one- and two-dimensional Poisson's equations. Using these models, we calculate the bottom potential of the channel and the threshold voltage shift, which characterize the DIBL effect. The calculated results reveal that the DMG structure alleviates the deterioration of the threshold voltage and thus suppresses the DIBL effect due to the introduced step function which originates from the work function difference of the two gate materials when compared with the conventional single material gate metal-semiconductor field-effect transistor (SMGFET).

Keywords: silicon carbide metal-semiconductor contact dual material gate

Received: 03 January 2012
Revised: 23 March 2012
Accepted manuscript online:

PACS:	73.40.Jn	(Metal-to-metal contacts)
	85.30.Tv	(Field effect devices)
	85.30.De	(Semiconductor-device characterization, design, and modeling)

Fund: Project supported by the Pre-research Foundation from the National Ministries and Commissions of China (Grant No. 51308030201).

Corresponding Authors: Zhang Xian-Jun
E-mail: xianjun_zhang@yahoo.com.cn

Cite this article:

Zhang Xian-Jun (张现军), Yang Yin-Tang (杨银堂), Duan Bao-Xing (段宝兴), Chai Chang-Chun (柴常春), Song Kun (宋坤), Chen Bin (陈斌) Drain-induced barrier lowering effect for short channel dual material gate 4H silicon carbide metal–semiconductor field-effect transistor 2012 Chin. Phys. B 21 097302

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Drain-induced barrier lowering effect for short channel dual material gate 4H silicon carbide metal–semiconductor field-effect transistor

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