Analysis of the breakdown mechanism for an ultra high voltage high-side thin layer silicon-on-insulator p-channel lateral double-diﬀused metal oxide semiconductor

doi:10.1088/1674-1056/21/3/037305

Abstract This paper discusses the breakdown mechanism and proposes a new simulation and test method of breakdown voltage (BV) for an ultra-high-voltage (UHV) high-side thin layer silicon-on-insulator (SOI) p-channel lateral double-di?used metal oxide semiconductor (LDMOS). Compared with the conventional simulation method, the new one is more accordant with the actual conditions of a device that can be used in the high voltage circuit. The BV of the SOI p-channel LDMOS can be properly represented and the effect of reduced bulk field can be revealed by employing the new simulation method. Simulation results show that the off-state (on-state) BV of the SOI p-channel LDMOS can reach 741 (620) V in the 3-μm-thick buried oxide layer, 50-μm-length drift region, and at -400 V back-gate voltage, enabling the device to be used in a 400 V UHV integrated circuit.

Keywords: silicon on insulator breakdown voltage back-gate voltage lateral double-diffused metal oxide semiconductor

Received: 24 July 2011
Revised: 08 October 2011
Accepted manuscript online:

PACS:	73.40.Ty	(Semiconductor-insulator-semiconductor structures)
	73.90.+f	(Other topics in electronic structure and electrical properties of surfaces, interfaces, thin films, and low-dimensional structures)
	73.61.Ng	(Insulators)

Fund: Project supported by the National Natural Science Foundation of China (Grant No. 60906038).

Corresponding Authors: Zhuang Xiang,zhuangxiang19861226@126.com
E-mail: zhuangxiang19861226@126.com

Cite this article:

Zhuang Xiang(庄翔), Qiao Ming(乔明), Zhang Bo(张波), and Li Zhao-Ji(李肇基) Analysis of the breakdown mechanism for an ultra high voltage high-side thin layer silicon-on-insulator p-channel lateral double-diﬀused metal oxide semiconductor 2012 Chin. Phys. B 21 037305

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Analysis of the breakdown mechanism for an ultra high voltage high-side thin layer silicon-on-insulator p-channel lateral double-diﬀused metal oxide semiconductor

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