The breakdown mechanism of a high-side pLDMOS based on a thin-layer silicon-on-insulator structure

doi:10.1088/1674-1056/21/1/018501

Abstract A high-side thin-layer silicon-on-insulator (SOI) pLDMOS is proposed, adopting field implant (FI) and multiple field plate (MFP) technologies. The breakdown mechanisms of back gate (BG) turn-on, surface channel punch-through, and vertical and lateral avalanche breakdown are investigated by setting up analytical models, simulating related parameters and verifying experimentally. The device structure is optimized based on the above research. The shallow junction achieved through FI technology attenuates the BG effect, the optimized channel length eliminates the surface channel punch-through, the advised thickness of the buried oxide dispels the vertical avalanche breakdown, and the MFP technology avoids premature lateral avalanche breakdown by modulating the electric field distribution. Finally, for the first time, a 300 V high-side pLDMOS is experimentally realized on a 1.5 μ m thick thin-layer SOI.

Keywords: field implant technology back gate punch-through surface channel punch-through avalanche breakdown

Received: 17 June 2011
Revised: 18 July 2011
Accepted manuscript online:

PACS:	85.30.De	(Semiconductor-device characterization, design, and modeling)
	85.30.Tv	(Field effect devices)
	84.70.+p	(High-current and high-voltage technology: power systems; power transmission lines and cables)

Fund: Project supported by National Natural Science Foundation of China (Grant No. 60906038).

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Zhao Yuan-Yuan(赵远远), Qiao Ming(乔明), Wang Wei-Bin(王伟宾), Wang Meng(王猛), and Zhang Bo(张波) The breakdown mechanism of a high-side pLDMOS based on a thin-layer silicon-on-insulator structure 2012 Chin. Phys. B 21 018501

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The breakdown mechanism of a high-side pLDMOS based on a thin-layer silicon-on-insulator structure

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