Effect of STI-induced mechanical stress on leakage current in deep submicron CMOS devices
Li Rui(李睿)a)b)c)†, Yu Liu-Jiang(俞柳江)c), Dong Ye-Min(董业民)c), and Wang Ching-Dong(王庆东)c)
a Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050, China; b Graduate School of Chinese Academy of Sciences, Beijing 100049, China;c Grace Semiconductor Manufacturing Corporation, Shanghai 201203, China
Abstract The shallow trench isolation (STI) induced mechanical stress significantly affects the CMOS device off-state leakage behaviour. In this paper, we designed two types of devices to investigate this effect, and all leakage components, including sub-threshold leakage ($I_{\rm sub})$, gate-induced-drain-leakage ($I_{\rm GIDL})$, gate edge-direct-tunnelling leakage ($I_{\rm EDT})$ and band-to-band-tunnelling leakage ($I_{\rm BTBT})$ were analysed. For NMOS, $I_{\rm sub}$ can be reduced due to the mechanical stress induced higher boron concentration in well region. However, the GIDL component increases simultaneously as a result of the high well concentration induced drain-to-well depletion layer narrowing as well as the shrinkage of the energy gap. For PMOS, the only mechanical stress effect on leakage current is the energy gap narrowing induced GIDL increase.
Received: 12 December 2006
Revised: 10 January 2007
Accepted manuscript online:
(Semiconductor-device characterization, design, and modeling)
Cite this article:
Li Rui(李睿), Yu Liu-Jiang(俞柳江), Dong Ye-Min(董业民), and Wang Ching-Dong(王庆东) Effect of STI-induced mechanical stress on leakage current in deep submicron CMOS devices 2007 Chinese Physics 16 3104
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