Critical area computation for real defects and arbitrary conductor shapes
Wang Jun-Ping (王俊平), Hao Yue (郝跃)
Microelectronics Institute, Xidian University, Xi'an 710071, China;Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, Xidian University, Xi'an 710071, China
Abstract In current critical area models, it is generally assumed the defect outlines are circular and the conductors to be rectangle or the merger of rectangles. However, real defects and conductors associated with optimal layout design exhibit a great variety of shapes. Based on mathematical morphology, a new critical area model is presented, which can be used to estimate the critical area of short circuit, open circuit and pinhole. Based on the new model, the efficient validity check algorithms are explored to extract critical areas of short circuit, open circuit and pinhole from layouts. The results of experiment on an approximate layout of ${4\times 4}$ shifts register show that the new model predicts the critical areas accurately. These results suggest that the proposed model and algorithm could provide new approaches for yield prediction.
Received: 09 December 2005
Revised: 17 April 2006
Accepted manuscript online:
PACS:
85.40.Bh
(Computer-aided design of microcircuits; layout and modeling)
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