a Microelectronics Institute, Xidian University, Xi'an 710071, China; b Key Laboratory of Ministry of Education for Wide Band-gap Semiconductor Materials and Devices,Xidian University, Xi'an 710071, Chinac Microelectronics Institute, Chinese Academy of Sciences, Beijing 100029, China; d School of Design, Engineering and Computing, Bournemouth University, UK
Abstract N and P-channel groove-gate MOSFETs based on a self-aligned CMOS process have been fabricated and characterized. For the devices with channel length of 140nm, the measured drain induced barrier lowering (DIBL) was 66mV/V for n-MOSFETs and 82mV/V for p-MOSFETs. The substrate current of a groove-gate n-MOSFET was 150 times less than that of a conventional planar n-MOSFET. These results demonstrate that groove-gate MOSFETs have excellent capabilities in suppressing short-channel effects. It is worth emphasizing that our groove-gate MOSFET devices are fabricated by using a simple process flow, with the potential of fabricating devices in the sub-100nm range.
Received: 29 March 2005
Revised: 09 September 2005
Accepted manuscript online:
Fund: Project supported by the National Natural Science Foundation of China (Grant No 60376024).
Cite this article:
Ma Xiao-Hua (马晓华), Hao Yue (郝跃), Sun Bao-Gang (孙宝刚), Gao Hai-Xia (高海霞), Ren Hong-Xia (任红霞), Zhang Jin-Cheng (张进城), Zhang Jin-Feng (张金凤), Zhang Xiao-Ju (张晓菊), Zhang Wei-Dong (张卫东) Fabrication and characterization of groove-gate MOSFETs based on a self-aligned CMOS process 2006 Chinese Physics 15 195
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